MC68HC908AB32CFU Freescale Semiconductor, MC68HC908AB32CFU Datasheet - Page 321

• Manufacturer Part Number: MC68HC908AB32CFU
• Description: IC MCU 8MHZ 32K FLASH 64-QFP
• Manufacturer: Freescale Semiconductor
• Series: HC08r

Specifications of MC68HC908AB32CFU

• Core Processor: HC08
• Core Size: 8-Bit
• Speed: 8MHz
• Connectivity: SCI, SPI
• Peripherals: POR, PWM
• Number Of I /o: 51
• Program Memory Size: 32KB (32K x 8)
• Program Memory Type: FLASH
• Eeprom Size: 512 x 8
• Ram Size: 1K x 8
• Voltage - Supply (vcc/vdd): 4.5 V ~ 5.5 V
• Data Converters: A/D 8x8b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 64-QFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant

17.5.2 Data Direction Register C (DDRC)
MC68HC908AB32
Freescale Semiconductor
NOTE:
—
Rev. 1.1
Address:
PTC[5:0] — Port C Data Bits
MCLK — T12 System Clock
Data direction register C determines whether each port C pin is an input
or an output. Writing a logic 1 to a DDRC bit enables the output buffer for
the corresponding port C pin; a logic 0 disables the output buffer.
MCLKEN — T12 System Clock Enable Bit
DDRC[5:0] — Data Direction Register C Bits
Avoid glitches on port C pins by writing to the port C data register before
changing data direction register C bits from 0 to 1.
the port C I/O logic.
Reset:
Read:
Write:
These read/write bits are software programmable. Data direction of
each port C pin is under the control of the corresponding bit in data
direction register C. Reset has no effect on port C data.
The system clock is driven out of the PTC2 pin when MCLKEN is set.
This read/write bit enables MCLK to be an output signal on PTC2 pin.
Reset clears MCLKEN.
These read/write bits control port C data direction. Reset clears
DDRC[5:0], configuring all port C pins as inputs.
1 = PTC2 pin configured as MCLK output
0 = PTC2 pin configured as standard I/O pin
1 = Corresponding port C pin configured as output
0 = Corresponding port C pin configured as input
MCLKEN
$0006
Bit 7
0
Figure 17-9. Data Direction Register B (DDRB)
Input/Output (I/O) Ports
6
0
0
DDRC5
5
0
DDRC4
4
0
DDRC3
3
0
DDRC2
Figure 17-10
2
0
Input/Output (I/O) Ports
DDRC1
1
0
Technical Data
shows
DDRC0
Bit 0
0
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