MC68HC908AB32CFU Freescale Semiconductor, MC68HC908AB32CFU Datasheet - Page 270

• Manufacturer Part Number: MC68HC908AB32CFU
• Description: IC MCU 8MHZ 32K FLASH 64-QFP
• Manufacturer: Freescale Semiconductor
• Series: HC08r

Specifications of MC68HC908AB32CFU

• Core Processor: HC08
• Core Size: 8-Bit
• Speed: 8MHz
• Connectivity: SCI, SPI
• Peripherals: POR, PWM
• Number Of I /o: 51
• Program Memory Size: 32KB (32K x 8)
• Program Memory Type: FLASH
• Eeprom Size: 512 x 8
• Ram Size: 1K x 8
• Voltage - Supply (vcc/vdd): 4.5 V ~ 5.5 V
• Data Converters: A/D 8x8b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 64-QFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant

Serial Communications Interface
Technical Data
270
TC — Transmission Complete Bit
SCRF — SCI Receiver Full Bit
IDLE — Receiver Idle Bit
OR — Receiver Overrun Bit
This read-only bit is set when the SCTE bit is set, and no data,
preamble, or break character is being transmitted. TC generates an
SCI transmitter CPU interrupt request if the TCIE bit in SCC2 is also
set. TC is automatically cleared when data, preamble or break is
queued and ready to be sent. There may be up to 1.5 transmitter
clocks of latency between queueing data, preamble, and break and
the transmission actually starting. Reset sets the TC bit.
This clearable, read-only bit is set when the data in the receive shift
register transfers to the SCI data register. SCRF can generate an SCI
receiver CPU interrupt request. When the SCRIE bit in SCC2 is set,
SCRF generates a CPU interrupt request. In normal operation, clear
the SCRF bit by reading SCS1 with SCRF set and then reading the
SCDR. Reset clears SCRF.
This clearable, read-only bit is set when 10 or 11 consecutive logic 1s
appear on the receiver input. IDLE generates an SCI error CPU
interrupt request if the ILIE bit in SCC2 is also set. Clear the IDLE bit
by reading SCS1 with IDLE set and then reading the SCDR. After the
receiver is enabled, it must receive a valid character that sets the
SCRF bit before an idle condition can set the IDLE bit. Also, after the
IDLE bit has been cleared, a valid character must again set the SCRF
bit before an idle condition can set the IDLE bit. Reset clears the IDLE
bit.
This clearable, read-only bit is set when software fails to read the
SCDR before the receive shift register receives the next character.
The OR bit generates an SCI error CPU interrupt request if the ORIE
Serial Communications Interface Module (SCI)
1 = No transmission in progress
0 = Transmission in progress
1 = Received data available in SCDR
0 = Data not available in SCDR
1 = Receiver input idle
0 = Receiver input active (or idle since the IDLE bit was cleared)
MC68HC908AB32
Freescale Semiconductor
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Rev. 1.1