MC68HC705P6ACP Freescale Semiconductor, MC68HC705P6ACP Datasheet - Page 31

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MC68HC705P6ACP

Manufacturer Part Number
MC68HC705P6ACP
Description
IC MCU 2.1MHZ 4.5K OTP 28-DIP
Manufacturer
Freescale Semiconductor
Series
HC05r
Datasheet

Specifications of MC68HC705P6ACP

Core Processor
HC05
Core Size
8-Bit
Speed
2.1MHz
Connectivity
SIO
Peripherals
POR, WDT
Number Of I /o
21
Program Memory Size
4.5KB (4.5K x 8)
Program Memory Type
OTP
Ram Size
176 x 8
Voltage - Supply (vcc/vdd)
3 V ~ 5.5 V
Data Converters
A/D 4x8b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
28-DIP (0.600", 15.24mm)
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Eeprom Size
-

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Chapter 4
Resets
4.1 Introduction
The MCU can be reset from three sources: one external input and two internal reset conditions. The
RESET pin is a Schmitt trigger input as shown in
reset by the RST signal which is the logical OR of internal reset functions and is clocked by PH1.
4.2 External Reset (RESET)
The RESET input is the only external reset and is connected to an internal Schmitt trigger. The external
reset occurs whenever the RESET input is driven below the lower threshold and remains in reset until the
RESET pin rises above the upper threshold. The upper and lower thresholds are given in
Electrical
4.3 Internal Resets
The two internally generated resets are the initial power-on reset (POR) function and the computer
operating properly (COP) watchdog timer function.
4.3.1 Power-On Reset (POR)
The internal POR is generated at power-up to allow the clock oscillator to stabilize. The POR is strictly for
power turn-on conditions and should not be used to detect a drop in the power supply voltage. There is a
4064 internal clock cycle oscillator stabilization delay after the oscillator becomes active.
Freescale Semiconductor
Specifications.
ADDRESS
RESET
DATA
OSC
V
DD
MC68HC705P6A Advance Information Data Sheet, Rev. 2.1
POWER-ON
WATCHDOG
RESET
(COPR)
(POR)
COP
Figure 4-1. Reset Block Diagram
Figure
4-1. The CPU and all peripheral modules will be
RES
PH1
DFF
D
RST
TO CPU AND
PERIPHERALS
Chapter 14
31

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