MC68HC705P6ACDW Freescale Semiconductor, MC68HC705P6ACDW Datasheet - Page 32

• Manufacturer Part Number: MC68HC705P6ACDW
• Description: IC MCU 2.1MHZ 4.5K OTP 28-SOIC
• Manufacturer: Freescale Semiconductor
• Series: HC05r

Specifications of MC68HC705P6ACDW

• Core Processor: HC05
• Core Size: 8-Bit
• Speed: 2.1MHz
• Connectivity: SIO
• Peripherals: POR, WDT
• Number Of I /o: 21
• Program Memory Size: 4.5KB (4.5K x 8)
• Program Memory Type: OTP
• Ram Size: 176 x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 5.5 V
• Data Converters: A/D 4x8b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 28-SOIC (7.5mm Width)
• Data Bus Width: 8 bit
• Data Ram Size: 176 B
• Maximum Clock Frequency: 2.1 MHz
• Number Of Programmable I/os: 37
• Number Of Timers: 16 bit
• Operating Supply Voltage: 3.3 V to 5 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 8 bit
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: No RoHS Version Available

Resets
The POR will generate the RST signal and reset the MCU. If any other reset function is active at the end
of this 4064 internal clock cycle delay, the RST signal will remain active until the other reset condition(s)
end.
4.3.2 Computer Operating Properly (COP) Reset
When the COP watchdog timer is enabled (COP bit in the MOR is set), the internal COP reset is
generated automatically by a timeout of the COP watchdog timer. This timer is implemented with an
18-stage ripple counter that provides a timeout period of 65.5 ms when a 4-MHz oscillator is used. The
COP watchdog counter is cleared by writing a logical 0 to bit zero at location $1FF0.
The COP watchdog timer can be disabled by clearing the COP bit in the MOR or by applying 2 x V
the IRQ/V
operating voltage range (between V
bit in the mask option register (MOR) is set.
The COP register is shared with the least significant byte (LSB) of an unused vector address as shown
in
usually 0. Writing to this location will clear the COP watchdog timer.
When the COP watchdog timer expires, it will generate the RST signal and reset the MCU. If any other
reset function is active at the end of the COP reset signal, the RST signal will remain in the reset condition
until the other reset condition(s) end. When the reset condition ends, the MCU’s operating mode will be
selected (see
32
Figure
4-2. Reading this location will return the programmed value of the unused user interrupt vector,
PP
pin (for example, during bootloader). When the IRQ/V
Table 3-1. Operating Mode Conditions After
Address:
Read:
Write:
$1FF0
Figure 4-2. Unused Vector and COP Watchdog Timer
Bit 7
0
MC68HC705P6A Advance Information Data Sheet, Rev. 2.1
= Unimplemented
6
0
SS
–V
DD
5
0
), the COP watchdog timer’s output will be restored if the COP
4
0
Reset).
3
0
PP
2
0
pin is returned to its normal
1
0
Freescale Semiconductor
COPR
Bit 0
0
DD
to