ST7FMC1K2TCE STMicroelectronics, ST7FMC1K2TCE Datasheet - Page 218

• Manufacturer Part Number: ST7FMC1K2TCE
• Description: IC MCU 8BIT 8K FLASH 32-LQFP
• Manufacturer: STMicroelectronics
• Series: ST7r

Specifications of ST7FMC1K2TCE

• Core Processor: ST7
• Core Size: 8-Bit
• Speed: 8MHz
• Connectivity: LINSCI
• Peripherals: LVD, Motor Control PWM, POR, PWM, WDT
• Number Of I /o: 17
• Program Memory Size: 8KB (8K x 8)
• Program Memory Type: FLASH
• Ram Size: 384 x 8
• Voltage - Supply (vcc/vdd): 3.8 V ~ 5.5 V
• Data Converters: A/D 16x10b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 125°C
• Package / Case: 32-LQFP
• For Use With: 497-8402 - BOARD EVAL COMPLETE INVERTER497-8400 - KIT IGBT PWR MODULE CTRL ST7MC497-4734 - EVAL KIT 3KW POWER DRIVER BOARD497-4733 - EVAL KIT 1KW POWER DRIVER BOARD497-4732 - EVAL KIT 300W POWER DRIVER BOARD497-4731 - EVAL KIT PWR DRIVER CONTROL BRD
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

ST7MC1xx/ST7MC2xx
MOTOR CONTROLLER (Cont’d)
PWM CONTROL REGISTER (MPCR)
Read/Write
Reset Value: 0000 0000 (00h)
Bit 7 = PMS: PWM Mode Selection.
0: Standard mode: bit b7 in the MCPxH register
1: “8-bit” mode: bit b7 (extension bit) in the MCPxH
Bit 6 = OVFU: Phase U 100% duty cycle Selec-
tion.
0: Duty cycle defined by MCPUH:MCPUL register.
1: Duty cycle set at 100% on phase U at next up-
Bit 5 = OVFV: Phase V 100% duty cycle Selection.
0: Duty cycle defined by MCPVH:MCPVL register.
1: Duty cycle set at 100% on phase V at next up-
218/309
PMS
represents the extension bit.
register is located in the MPCR register (OVFx
bits); the number of active bits in MCPxH and
MCPxL is decreased to b15:b8 instead of
b15:b3.
date event and maintained till the next one. This
bit is reset once transferred to the active register
on update event.
date event and maintained till the next one. This
bit is reset once transferred to the active register
on update event.
7
OVFU OVFV OVFW CMS PCP2
PCP1
PCP0
0
Bit 4 = OVFW: Phase W 100% duty cycle Selec-
tion.
0: Duty cycle defined by MCPWH:MCPWL regis-
1: Duty cycle set at 100% on phase W at next up-
Bit 3 = CMS: PWM Counter Mode Selection.
0: Edge-aligned mode
1: Center-aligned mode
Bits 2:0 = PCP[2:0] PWM counter prescaler value.
This value divides the F
N is PCP[2:0] value.
frequency of the PWM counter input clock.
Table 73. PWM clock prescaler
PCP2
ter.
date event and maintained till the next one. This
bit is reset once transferred to the active register
on update event.
0
0
0
0
1
1
1
1
PCP1
0
0
1
1
0
0
1
1
PCP0 PWM counter input clock
0
1
0
1
0
1
0
1
Table 73
mtc
frequency by N, where
shows the resulting
F
F
F
F
F
F
F
F
mtc
mtc
mtc
mtc
mtc
mtc
mtc
mtc
/2
/3
/4
/5
/6
/7
/8