ZLP32300H4832G Zilog, ZLP32300H4832G Datasheet - Page 51

• Manufacturer Part Number: ZLP32300H4832G
• Description: IC CRIMZON Z8 MCU OTP 32K 48SSOP
• Manufacturer: Zilog
• Series: Crimzon™ ZLPr

Specifications of ZLP32300H4832G

• Core Processor: Z8
• Core Size: 8-Bit
• Speed: 8MHz
• Peripherals: Brown-out Detect/Reset, HLVD, POR, WDT
• Number Of I /o: 32
• Program Memory Size: 32KB (32K x 8)
• Program Memory Type: OTP
• Ram Size: 237 x 8
• Voltage - Supply (vcc/vdd): 2 V ~ 3.6 V
• Oscillator Type: Internal
• Operating Temperature: 0°C ~ 70°C
• Package / Case: 48-SSOP
• Data Bus Width: 8 bit
• Data Ram Size: 237 B
• Maximum Clock Frequency: 8 MHz
• Number Of Programmable I/os: 32
• Number Of Timers: 2
• Operating Supply Voltage: 2 V to 3.6 V
• Maximum Operating Temperature: + 70 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: 0 C
• For Use With: 269-4665 - KIT REMOTE UNVRSL USA 6-FUNCTION
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Data Converters: -
• Connectivity: -
• Lead Free Status / Rohs Status: Details
• Other names: 269-4510; ZLP32300H4832G

PS020823-0208
Power Management
For both resonator and crystal oscillator, the oscillation ground must go directly to the
ground pin of the microcontroller. The oscillation ground must use the shortest distance
from the microcontroller ground pin and it must be isolated from other connections.
Power-On Reset
A timer circuit clocked by a dedicated on-board RC-oscillator is used for the Power-On
Reset timer function. The POR time allows V
before instruction execution begins.
The POR timer circuit is a one-shot timer triggered by one of three conditions:
•
•
•
The POR timer is 2.5 ms minimum. Bit 5 of the Stop Mode Register determines whether
the POR timer is bypassed after Stop Mode Recovery (typical for external clock).
HALT Mode
This instruction turns off the internal CPU clock, but not the XTAL oscillation. The
counter/timers and external interrupts IRQ0, IRQ1, IRQ2, IRQ3, IRQ4, and IRQ5 remain
active. The devices are recovered by interrupts, either externally or internally generated.
An interrupt request must be executed (enabled) to exit HALT Mode. After the interrupt
service routine, the program continues from the instruction after HALT Mode.
STOP Mode
This instruction turns OFF the internal clock and external crystal oscillation, reducing the
standby current to 10 µA or less. STOP mode is terminated only by a reset, such as WDT
time-out, POR or SMR. This condition causes the processor to restart the application pro-
gram at address
line to avoid suspending execution in mid-instruction. Execute a NOP (Opcode =
immediately before the appropriate sleep instruction, as follows:
or
Power Fail to Power OK status, including Waking up from V
Stop Mode Recovery (if D5 of SMR = 1)
WDT Timeout
FF
6F
FF
7F
000Ch
NOP
STOP
NOP
HALT
. To enter STOP (or HALT) mode, first flush the instruction pipe-
; clear the pipeline
; enter Stop Mode
; clear the pipeline
; enter HALT Mode
DD
and the oscillator circuit to stabilize
Product Specification
BO
Crimzon
Standby
Functional Description
®
ZLP32300
FFh
)
47