ZLP32300H4832G Zilog, ZLP32300H4832G Datasheet - Page 14

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ZLP32300H4832G

Manufacturer Part Number
ZLP32300H4832G
Description
IC CRIMZON Z8 MCU OTP 32K 48SSOP
Manufacturer
Zilog
Series
Crimzon™ ZLPr
Datasheets

Specifications of ZLP32300H4832G

Core Processor
Z8
Core Size
8-Bit
Speed
8MHz
Peripherals
Brown-out Detect/Reset, HLVD, POR, WDT
Number Of I /o
32
Program Memory Size
32KB (32K x 8)
Program Memory Type
OTP
Ram Size
237 x 8
Voltage - Supply (vcc/vdd)
2 V ~ 3.6 V
Oscillator Type
Internal
Operating Temperature
0°C ~ 70°C
Package / Case
48-SSOP
Data Bus Width
8 bit
Data Ram Size
237 B
Maximum Clock Frequency
8 MHz
Number Of Programmable I/os
32
Number Of Timers
2
Operating Supply Voltage
2 V to 3.6 V
Maximum Operating Temperature
+ 70 C
Mounting Style
SMD/SMT
Minimum Operating Temperature
0 C
For Use With
269-4665 - KIT REMOTE UNVRSL USA 6-FUNCTION
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Data Converters
-
Connectivity
-
Lead Free Status / Rohs Status
 Details
Other names
269-4510
ZLP32300H4832G
Pin Functions
PS020823-0208
Caution:
XTAL1 Crystal 1 (Time-Based Input)
XTAL2 Crystal 2 (Time-Based Output)
Input/Output Ports
Table 5. 40- and 48-Pin Configuration (Continued)
This pin connects a parallel-resonant crystal or ceramic resonator to the on-chip oscillator
input. Additionally, an optional external single-phase clock can be coded to the on-chip
oscillator input.
This pin connects a parallel-resonant crystal or ceramic resonant to the on-chip oscillator
output.
40-Pin PDIP No
The CMOS input buffer for each Port 0, 1, or 2 pin is always connected to the pin, even
when the pin is configured as an output. If the pin is configured as an open-drain output
and no external signal is applied, a High output state can cause the CMOS input buffer
to float. This might lead to excessive leakage current of more than 100 µA. To prevent
this leakage, connect the pin to an external signal with a defined logic level or ensure
its output state is Low, especially during STOP mode.
Internal pull-ups are disabled on any given pin or group of port pins when programmed
into output mode.
Port 0, 1, and 2 have both input and output capability. The input logic is always present
no matter whether the port is configured as input or output. When doing a READ in-
struction, the MCU reads the actual value at the input logic but not from the output buff-
er. In addition, the instructions of OR, AND, and XOR have the Read-Modify-Write
sequence. The MCU first reads the port, and then modifies the value and load back to
the port.
Precaution must be taken if the port is configured as open-drain output or if the port is
driving any circuit that makes the voltage different from the desired output logic. For
example, pins P00–P07 are not connected to anything else. If it is configured as
48-Pin SSOP No
14
30
36
Symbol
NC
NC
NC
Product Specification
Crimzon
®
Pin Description
ZLP32300
10

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