ZLP32300H4832G Zilog, ZLP32300H4832G Datasheet - Page 35

• Manufacturer Part Number: ZLP32300H4832G
• Description: IC CRIMZON Z8 MCU OTP 32K 48SSOP
• Manufacturer: Zilog
• Series: Crimzon™ ZLPr

Specifications of ZLP32300H4832G

• Core Processor: Z8
• Core Size: 8-Bit
• Speed: 8MHz
• Peripherals: Brown-out Detect/Reset, HLVD, POR, WDT
• Number Of I /o: 32
• Program Memory Size: 32KB (32K x 8)
• Program Memory Type: OTP
• Ram Size: 237 x 8
• Voltage - Supply (vcc/vdd): 2 V ~ 3.6 V
• Oscillator Type: Internal
• Operating Temperature: 0°C ~ 70°C
• Package / Case: 48-SSOP
• Data Bus Width: 8 bit
• Data Ram Size: 237 B
• Maximum Clock Frequency: 8 MHz
• Number Of Programmable I/os: 32
• Number Of Timers: 2
• Operating Supply Voltage: 2 V to 3.6 V
• Maximum Operating Temperature: + 70 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: 0 C
• For Use With: 269-4665 - KIT REMOTE UNVRSL USA 6-FUNCTION
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Data Converters: -
• Connectivity: -
• Lead Free Status / Rohs Status: Details
• Other names: 269-4510; ZLP32300H4832G

Table 9. CTR2(D)02h: Counter/Timer16 Control Register
PS020823-0208
Field
T16_Enable
Single/Modulo-N
Time_Out
Note:
Initial_T8_Out/Rising_Edge
In TRANSMIT mode, if 0, the output of T8 is set to 0 when it starts to count. If 1, the out-
put of T8 is set to 1 when it starts to count. When the counter is not enabled and this bit is
set to 1 or 0, T8_OUT is set to the opposite state of this bit. This ensures that when the
clock is enabled, a transition occurs to the initial state set by CTR1, D1.
In DEMODULATION mode, this bit is set to 1 when a rising edge is detected in the input
signal. In order to reset the mode, a 1 should be written to this location.
Initial_T16 Out/Falling _Edge
In TRANSMIT mode, if it is 0, the output of T16 is set to 0 when it starts to count. If it is
1, the output of T16 is set to 1 when it starts to count. This bit is effective only in Normal
or PING-PONG mode (CTR1, D3; D2). When the counter is not enabled and this bit is set,
T16_OUT is set to the opposite state of this bit. This ensures that when the clock is
enabled, a transition occurs to the initial state set by CTR1, D0.
In DEMODULATION mode, this bit is set to 1 when a falling edge is detected in the input
signal. In order to reset it, a 1 should be written to this location.
Modifying CTR1 (D1 or D0) while the counters are enabled causes unpredictable output
from T8/16_OUT.
CTR2 Counter/Timer 16 Control Register—CTR2(D)02h
Table 9
lists and briefly describes the fields for this register.
Bit Position
7-------
-6------
--5-----
R
W
R/W
R
W
0*
1
0
1
0*
1
0
1
0*
1
0
1
Value
Description
Counter Disabled
Counter Enabled
Stop Counter
Enable Counter
TRANSMIT Mode
Modulo-N
Single Pass
DEMODULATION Mode
T16 Recognizes Edge
T16 Does Not Recognize
Edge
No Counter Timeout
Counter Timeout
Occurred
No Effect
Reset Flag to 0
Product Specification
Crimzon
Functional Description
®
ZLP32300
31