Z8F6401AN020SC00TR Zilog, Z8F6401AN020SC00TR Datasheet - Page 181

• Manufacturer Part Number: Z8F6401AN020SC00TR
• Description: IC ENCORE MCU FLASH 64K 44LQFP
• Manufacturer: Zilog
• Series: Encore!®r

Specifications of Z8F6401AN020SC00TR

• Core Processor: Z8
• Core Size: 8-Bit
• Speed: 20MHz
• Connectivity: I²C, IrDA, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, DMA, POR, PWM, WDT
• Number Of I /o: 31
• Program Memory Size: 64KB (64K x 8)
• Program Memory Type: FLASH
• Ram Size: 4K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: 0°C ~ 70°C
• Package / Case: 44-LQFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -
• Other names: Z8F6401AN020SC00T

Table 96. OCD Watchpoint Control/Address (WPTCTL)
PS017610-0404
RESET
FIELD
BITS
R/W
OCD Watchpoint Control Register
WPW
R/W
RPEN—Read Protect Option Bit Enabled
0 = The Read Protect Option Bit is disabled (1).
0 = The Read Protect Option Bit is enabled (0), disabling many OCD commands.
Reserved
These bits are always 0.
The OCD Watchpoint Control register is used to configure the debug Watchpoint.
WPW—Watchpoint Break on Write
This bit cannot be set if the Read Protect Option Bit is enabled.
0 = Watchpoint Break on Register File write is disabled.
1 = Watchpoint Break on Register File write is enabled.
WPR—Watchpoint Break on Read
This bit cannot be set if the Read Protect Option Bit is enabled.
0 = Watchpoint Break on Register File read is disabled.
1 = Watchpoint Break on Register File write is enabled.
WPDM—Watchpoint Data Match
If this bit is set, then the Watchpoint only generates a Debug Break if the data being read
or written matches the specified Watchpoint data. Either the WPR and/or WPW bits must
also be set for this bit to affect operation. This bit cannot be set if the Read Protect Option
Bit is enabled.
0 = Watchpoint Break on read and/or write does not require a data match.
1 = Watchpoint Break on read and/or write requires a data match.
Reserved
This bit is reserved and must be 0.
RADDR[11:8]—Register address
These bits specify the upper 4 bits of the Register File address to match when generating a
Watchpoint Debug Break. The full 12-bit Register File address is given by {WPTCTL3:0],
WPTADDR[7:0]}.
7
0
WPR
R/W
6
0
WPDM
R/W
5
0
Reserved
R/W
4
0
Z8F640x/Z8F480x/Z8F320x/Z8F240x/Z8F160x
R/W
3
0
WPTADDR[11:8]
R/W
2
0
R/W
On-Chip Debugger
1
0
Z8 Encore!
R/W
0
0
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