Z8F6401AN020SC00TR Zilog, Z8F6401AN020SC00TR Datasheet - Page 65
Z8F6401AN020SC00TR
Manufacturer Part Number
Z8F6401AN020SC00TR
Description
IC ENCORE MCU FLASH 64K 44LQFP
Manufacturer
Zilog
Series
Encore!®r
Datasheet
1.Z8F1601VN020EC.pdf
(246 pages)
Specifications of Z8F6401AN020SC00TR
Core Processor
Z8
Core Size
8-Bit
Speed
20MHz
Connectivity
I²C, IrDA, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, DMA, POR, PWM, WDT
Number Of I /o
31
Program Memory Size
64KB (64K x 8)
Program Memory Type
FLASH
Ram Size
4K x 8
Voltage - Supply (vcc/vdd)
3 V ~ 3.6 V
Data Converters
A/D 8x10b
Oscillator Type
Internal
Operating Temperature
0°C ~ 70°C
Package / Case
44-LQFP
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Eeprom Size
-
Other names
Z8F6401AN020SC00T
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Interrupt Vectors and Priority
Interrupt Assertion Types
•
•
The Z8F640x family device interrupt controller supports three levels of interrupt priority.
Level 3 is the highest priority, Level 2 is the second highest priority, and Level 1 is the
lowest priority. If all of the interrupts were enabled with identical interrupt priority (all as
Level 2 interrupts, for example), then interrupt priority would be assigned from highest to
lowest as specified in Table 22. Level 3 interrupts always have higher priority than Level 2
interrupts which, in turn, always have higher priority than Level 1 interrupts. Within each
interrupt priority level (Level 1, Level 2, or Level 3), priority is assigned as specified in
Table 22.
Reset, Watch-Dog Timer interrupt (if enabled), and Illegal Instruction Trap always have
highest (Level 3) priority.
Two types of interrupt assertion - single assertion (pulse) and continuous assertion - are
used within the Z8F640x family device. The type of interrupt assertion for each interrupt
source is listed in Table 22.
Single Assertion (Pulse) Interrupt Sources
Some interrupt sources assert their interrupt requests for only a single system clock period
(single pulse). When the interrupt request is acknowledged by the eZ8 CPU, the corre-
sponding bit in the Interrupt Request register is cleared until the next interrupt occurs.
Writing a 0 to the corresponding bit in the Interrupt Request register likewise clears the
interrupt request.
Continuous Assertion Interrupt Sources
Other interrupt sources continuously assert their interrupt requests until cleared at the
source. For these continuous assertion interrupt sources, interrupt acknowledgement by
the eZ8 CPU does not clear the corresponding bit in the Interrupt Request register. Writing
a 0 to the corresponding bit in the Interrupt Request register only clears the interrupt for a
single clock cycle. Since the source is continuously asserting the interrupt request, the
interrupt request bit is set to 1 again during the next clock cycle.
The only way to clear continuous assertion interrupts is at the source of the interrupt (for
example, in the UART or SPI peripherals). The source of the interrupt must be cleared
first. After the interrupt is cleared at the source, the corresponding bit in the Interrupt
Request register must also be cleared to 0. Both the interrupt source and the IRQ register
must be cleared.
Execution of a Trap instruction
Illegal instruction trap
Z8F640x/Z8F480x/Z8F320x/Z8F240x/Z8F160x
Interrupt Controller
Z8 Encore!
®
47
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