Z8F6401AN020SC00TR Zilog, Z8F6401AN020SC00TR Datasheet - Page 109
Z8F6401AN020SC00TR
Manufacturer Part Number
Z8F6401AN020SC00TR
Description
IC ENCORE MCU FLASH 64K 44LQFP
Manufacturer
Zilog
Series
Encore!®r
Datasheet
1.Z8F1601VN020EC.pdf
(246 pages)
Specifications of Z8F6401AN020SC00TR
Core Processor
Z8
Core Size
8-Bit
Speed
20MHz
Connectivity
I²C, IrDA, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, DMA, POR, PWM, WDT
Number Of I /o
31
Program Memory Size
64KB (64K x 8)
Program Memory Type
FLASH
Ram Size
4K x 8
Voltage - Supply (vcc/vdd)
3 V ~ 3.6 V
Data Converters
A/D 8x10b
Oscillator Type
Internal
Operating Temperature
0°C ~ 70°C
Package / Case
44-LQFP
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Eeprom Size
-
Other names
Z8F6401AN020SC00T
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Table 56. UARTx Baud Rate High Byte Register (UxBRH)
PS017610-0404
RESET
FIELD
ADDR
BITS
R/W
UARTx Baud Rate High and Low Byte Registers
R/W
7
1
0 = Disable Multiprocessor mode.
1 = Enable Multiprocessor mode.
MPE—Multiprocessor Enable
0 = The UART processes all received data bytes.
1 = The UART processes only data bytes in which the multiprocessor data bit (9th bit) is
set to 1.
MPBT—Multiprocessor Bit Transmitter
This bit is applicable only when Multiprocessor (9-bit) mode is enabled.
0 = Send a 0 in the multiprocessor bit location of the data stream (9th bit).
1 = Send a 1 in the multiprocessor bit location of the data stream (9th bit).
Reserved
These bits are reserved and must be 0.
RDAIRQ—Receive Data Interrupt Enable
0 = Received data and receiver errors generates an interrupt request to the Interrupt Con-
troller.
1 = Received data does not generate an interrupt request to the Interrupt Controller. Only
receiver errors generate an interrupt request. The associated DMA will still be notified that
received data is available.
IREN—Infrared Encoder/Decoder Enable
0 = Infrared Encoder/Decoder is disabled. UART operates normally operation.
1 = Infrared Encoder/Decoder is enabled. The UART transmits and receives data through
the Infrared Encoder/Decoder.
The UARTx Baud Rate High and Low Byte registers (Tables 56 and 57) combine to create
a 16-bit baud rate divisor value (BRG[15:0]) that sets the data transmission rate (baud
rate) of the UART.
R/W
6
1
R/W
5
1
R/W
F46H and F4EH
4
1
Z8F640x/Z8F480x/Z8F320x/Z8F240x/Z8F160x
BRH
R/W
3
1
R/W
2
1
R/W
1
1
Z8 Encore!
R/W
0
1
UART
®
91
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