Z8F3201VN020EC00TR Zilog, Z8F3201VN020EC00TR Datasheet - Page 102

• Manufacturer Part Number: Z8F3201VN020EC00TR
• Description: IC ENCORE MCU FLASH 32K 44PLCC
• Manufacturer: Zilog
• Series: Encore!®r

Specifications of Z8F3201VN020EC00TR

• Core Processor: Z8
• Core Size: 8-Bit
• Speed: 20MHz
• Connectivity: I²C, IrDA, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, DMA, POR, PWM, WDT
• Number Of I /o: 31
• Program Memory Size: 32KB (32K x 8)
• Program Memory Type: FLASH
• Ram Size: 2K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 105°C
• Package / Case: 44-LCC (J-Lead)
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -
• Other names: Z8F3201VN020EC00T

Figure 70. UART Asynchronous Multiprocessor (9-bit) Mode Data Format
PS017610-0404
1
0
Idle State
of Line
Multiprocessor (9-bit) mode
6. Write to the UART Control 0 register to:
The UART and DMA are now configured for data reception and automatic data transfer to
the Register File. When a valid data byte is received by the UART the following occurs:
7. The UART notifies the DMA Controller that a data byte is available in the UART
8. The DMA Controller requests control of the system bus from the eZ8 CPU.
9. The eZ8 CPU acknowledges the bus request.
10. The DMA Controller transfers the data from the UART Receive Data register to
The UART and DMA can continue to transfer incoming data bytes without eZ8 CPU
intervention. When a UART error is detected, the UART Receiver interrupt is generated.
The associated interrupt service routine (ISR) should perform the following:
11. Check the UART Status 0 register to determine the source of the UART error or break
The UART has a Multiprocessor mode that uses an extra (9th) bit for selective communi-
cation when a number of processors share a common UART bus. In Multiprocessor (9-bit)
mode (also referred to as 9-Bit mode), the multiprocessor bit (MP) is transmitted immedi-
ately following the 8-bits of data and immediately preceding the STOP bit(s) as illustrated
in Figure 70. The character format is:
In Multiprocessor (9-bit) mode, parity is not an option as the Parity bit location (9th bit)
becomes the Multiprocessor control bit. The UART Control 1 and Status 1 registers pro-
vide multiprocessor (9-bit) mode control and status information.
Start
–
–
Receive Data register.
another location in RAM and then return bus control back to the eZ8 CPU.
condition and then respond appropriately.
Bit0
Set the receive enable bit (REN) to enable the UART for data reception
Enable parity, if desired, and select either even or odd parity.
lsb
Bit1
Bit2
Bit3
Data Field
Z8F640x/Z8F480x/Z8F320x/Z8F240x/Z8F160x
Bit4
Bit5
Bit6
msb
Bit7
MP
STOP Bit(s)
1
Z8 Encore!
2
UART
®
84