LH79524N0F100A1,55 NXP Semiconductors, LH79524N0F100A1,55 Datasheet - Page 30

• Manufacturer Part Number: LH79524N0F100A1,55
• Description: IC ARM7 BLUESTREAK MCU 208LFBGA
• Manufacturer: NXP Semiconductors
• Series: BlueStreak ; LH7r

Specifications of LH79524N0F100A1,55

• Core Processor: ARM7
• Core Size: 32-Bit
• Speed: 76.2MHz
• Connectivity: EBI/EMI, Ethernet, I²C, IrDA, Microwire, SPI, SSI, SSP, UART/USART, USB
• Peripherals: Brown-out Detect/Reset, DMA, I²S, LCD, POR, PWM, WDT
• Number Of I /o: 108
• Program Memory Type: ROMless
• Ram Size: 16K x 8
• Voltage - Supply (vcc/vdd): 1.7 V ~ 3.6 V
• Data Converters: A/D 10x10b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 208-LFBGA
• For Use With: SDK-LH79524-10-3216R - KIT DEVELOPMENT ZOOM SDK LH79524460-3474 - KIT DEV ZOOM STARTER FOR LH79524568-4305 - BOARD EVAL FOR LH79524
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Other names: 568-4272; 935285053551; LH79524N0F100A1-S

LH79524/LH79525
A[27:0]
D[31:0]
nCS[3:0]
nBLE
nWE
nOE
A[23:0]
D[31:0]
nCAS
nRAS
30
SIGNAL
Output 50 pF
Output 50 pF
Output 50 pF
Output 50 pF
Output 50 pF
Output 50 pF
Output 50 pF
Output 50 pF
Output 50 pF
Ouput 50 pF
TYPE LOAD
Input
Input
SYMBOL
ASYNCHRONOUS MEMORY INTERFACE SIGNALS
tDHWE
tDHBW
tDHOE
tASWE
SYNCHRONOUS MEMORY INTERFACE SIGNALS
tOHCA
tOHRA
tDSCS
tDSOE
tDHCS
tAHCS
tAHOE
tDHBR
tOVCA
tOVRA
tASCS
tDWE
tOHD
tOEV
tOVA
tOVD
tDSB
tAHB
tASB
tBLE
tWC
tISD
tIHD
tCW
tAW
tWR
tWP
tRC
tOE
tAV
tCB
tCS
tBV
tDB
tBR
tAB
tBP
Table 14. AC Signal Characteristics
NXP Semiconductors
3 × tHCLK – 5.0 ns
2 × tHCLK – 5.0 ns
Rev. 01 — 16 July 2007
tSDCLK/2 – 4.0 ns
tSDCLK/2 – 4.0 ns
tSDCLK/2 – 4.0 ns
tHCLK – 5.5 ns
tHCLK – 4.5 ns
tHCLK – 3.0 ns
tHCLK – 3.5 ns
tHCLK – 2.0 ns
tHCLK – 6.0 ns
tHCLK – 4.5 ns
tHCLK – 4.5 ns
tHCLK – 3.0 ns
tHCLK - 1.0 ns
tHCLK + 9 ns
tHCLK – 1 ns
tHCLK – 1 ns
14.0 ns
12.5 ns
12.0 ns
–2.0 ns
0.0 ns
0.0 ns
0.0 ns
5.0 ns
1.5 ns
MIN.
2 × tHCLK + 3.0 ns
2 × tHCLK + 0.5 ns
tSDCLK/2 + 4.5 ns
tSDCLK/2 + 7.0 ns
tSDCLK/2 + 4.0 ns
tSDCLK/2 + 4.5 ns
tHCLK + 1.5 ns
2 × tHCLK ns
2 × tHCLK
– 0.5 ns
2.5 ns
2.5 ns
1.5 ns
1.0 ns
MAX.
Write Cycle time
Read Cycle time
Data out hold to nWE release
Data out valid to nWE release
Data valid to nCSx release
Data valid to nOE release
Data valid to nBLEx release
nCSx release to data invalid
nOE release to data invalid
nCSx valid to Address valid
Address hold after nCSx release
Address hold after nOE release
Address valid to nCSx valid
nCSx valid to nWE release
nCSx valid to nBLE release
nCSx width
nCSx valid to nBLE valid
Address hold after nBLE release
Data out valid to nBLE release
Data in hold to nBLE release
Data out hold to nBLE release
Address hold to nBLE release
Address valid to nBLE release
Address valid to nBLE valid
nBLE width (read)
nBLE width (write)
Address valid to nWE valid
Address valid to nWE release
Address Hold to nWE release
Write Enable width
Ouput Enable width
nOE valid after nCSx valid
Address Valid
Output Data Valid
Output Data Hold
Input Data Setup
Input Data Hold
CAS Valid
CAS Hold
RAS Valid
RAS Hold
Preliminary data sheet
DESCRIPTION
System-on-Chip