P89LPC936FDH,529 NXP Semiconductors, P89LPC936FDH,529 Datasheet - Page 41

• Manufacturer Part Number: P89LPC936FDH,529
• Description: IC 80C51 MCU FLASH 16K 28-TSSOP
• Manufacturer: NXP Semiconductors
• Series: LPC900r

Specifications of P89LPC936FDH,529

• Core Processor: 8051
• Core Size: 8-Bit
• Speed: 18MHz
• Connectivity: I²C, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, LED, POR, PWM, WDT
• Number Of I /o: 26
• Program Memory Size: 16KB (16K x 8)
• Program Memory Type: FLASH
• Eeprom Size: 512 x 8
• Ram Size: 768 x 8
• Voltage - Supply (vcc/vdd): 2.4 V ~ 3.6 V
• Data Converters: A/D 8x8b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 28-TSSOP
• For Use With: 622-1014 - BOARD FOR LPC9XX TSSOP622-1008 - BOARD FOR LPC9103 10-HVSON622-1006 - SOCKET ADAPTER BOARDMCB900K - BOARD PROTOTYPE NXP 89LPC9EPM900K - EMULATOR/PROGRAMMER NXP P89LPC9568-1759 - EMULATOR DEBUGGER/PROGRMMR LPC9X568-1758 - BOARD EVAL FOR LPC93X MCU FAMILY
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 568-2012-5; 935277841529; P89LPC936FDH-S

NXP Semiconductors
P89LPC933_934_935_936
Product data sheet
8.21 I
The I
connected to the bus, and it has the following features:
A typical I
device provides a byte-oriented I
400 kHz.
2
Fig 15. I
•
•
•
•
•
•
C-bus serial interface
Bidirectional data transfer between masters and slaves
Multi master bus (no central master)
Arbitration between simultaneously transmitting masters without corruption of serial
data on the bus
Serial clock synchronization allows devices with different bit rates to communicate via
one serial bus
Serial clock synchronization can be used as a handshake mechanism to suspend and
resume serial transfer
The I
2
C-bus uses two wires (SDA and SCL) to transfer information between devices
2
2
2
C-bus may be used for test and diagnostic purposes.
C-bus configuration is shown in
C-bus configuration
I
2
C-bus
All information provided in this document is subject to legal disclaimers.
P1.3/SDA
Rev. 8 — 12 January 2011
P89LPC935
8-bit microcontroller with accelerated two-clock 80C51 core
P1.2/SCL
2
C-bus interface that supports data transfers up to
P89LPC933/934/935/936
OTHER DEVICE
WITH I
R
Figure
INTERFACE
P
2
C-BUS
15. The P89LPC933/934/935/936
R
P
OTHER DEVICE
WITH I
INTERFACE
2
C-BUS
002aab082
© NXP B.V. 2011. All rights reserved.
SDA
SCL
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