P89LPC932A1FA,129 NXP Semiconductors, P89LPC932A1FA,129 Datasheet - Page 21

• Manufacturer Part Number: P89LPC932A1FA,129
• Description: IC 80C51 MCU FLASH 8K 28-PLCC
• Manufacturer: NXP Semiconductors
• Series: LPC900r

Specifications of P89LPC932A1FA,129

• Core Processor: 8051
• Core Size: 8-Bit
• Speed: 18MHz
• Connectivity: I²C, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, LED, POR, PWM, WDT
• Number Of I /o: 26
• Program Memory Size: 8KB (8K x 8)
• Program Memory Type: FLASH
• Ram Size: 768 x 8
• Voltage - Supply (vcc/vdd): 2.4 V ~ 3.6 V
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 28-PLCC
• For Use With: OM6292 - DEMO BOARD PCA2125 RTCDB-TSSOP-LPC932 - BOARD FOR LPC932 TSSOP622-1014 - BOARD FOR LPC9XX TSSOP622-1008 - BOARD FOR LPC9103 10-HVSON622-1006 - SOCKET ADAPTER BOARDMCB900K - BOARD PROTOTYPE NXP 89LPC9EPM900K - EMULATOR/PROGRAMMER NXP P89LPC9622-1003 - KIT FOR LCD DEMO568-1759 - EMULATOR DEBUGGER/PROGRMMR LPC9X568-1758 - BOARD EVAL FOR LPC93X MCU FAMILY
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Data Converters: -
• Other names: 568-1285-5; 935276131129; P89LPC932A1FA-S

NXP Semiconductors
Table 5.
P89LPC932A1_3
Product data sheet
Clock source
On-chip oscillator or watchdog oscillator
Fig 8. Interrupt sources, interrupt enables, and power-down wake-up sources
(1) See
(RTCCON.1)
Number of I/O pins available
WDOVF
Section 7.19 “CCU”
RTCF
ERTC
7.13 I/O ports
In edge-triggered mode, if successive samples of the INTn pin show a HIGH in one cycle
and a LOW in the next cycle, the interrupt request flag IEn in TCON is set, causing an
interrupt request.
If an external interrupt is enabled when the P89LPC932A1 is put into Power-down or Idle
mode, the interrupt will cause the processor to wake-up and resume operation. Refer to
Section 7.15 “Power reduction modes”
The P89LPC932A1 has four I/O ports: Port 0, Port 1, Port 2, and Port 3. Ports 0, 1 and 2
are 8-bit ports, and Port 3 is a 2-bit port. The exact number of I/O pins available depends
upon the clock and reset options chosen, as shown in
any CCU interrupt
EA (IE0.7)
TI & RI/RI
ES/ESR
EWDRT
ECCU
CMF2
CMF1
KBIF
EKBI
EI2C
SPIF
ESPI
EEIF
EIEE
BOF
EBO
EST
EX0
EX1
ET0
ET1
TF0
TF1
IE0
IE1
EC
(1)
SI
TI
Reset option
No external reset (except during power-up)
External RST pin supported
Rev. 03 — 12 March 2007
8-bit microcontroller with accelerated two-clock 80C51 core
for details.
Table
P89LPC932A1
002aaa892
5.
Number of I/O pins
(28-pin package)
26
25
interrupt
to CPU
wake-up
(if in power-down)
© NXP B.V. 2007. All rights reserved.
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