ATTINY87-15XZ Atmel, ATTINY87-15XZ Datasheet - Page 213
![MCU AVR 8K FLASH 15MZ 20-TSSOP](/photos/6/80/68045/313-20-tssop_sml.jpg)
ATTINY87-15XZ
Manufacturer Part Number
ATTINY87-15XZ
Description
MCU AVR 8K FLASH 15MZ 20-TSSOP
Manufacturer
Atmel
Series
AVR® ATtinyr
Datasheet
1.ATTINY167-15MD.pdf
(283 pages)
Specifications of ATTINY87-15XZ
Core Processor
AVR
Core Size
8-Bit
Speed
16MHz
Connectivity
I²C, LIN, SPI, UART/USART, USI
Peripherals
Brown-out Detect/Reset, POR, PWM, Temp Sensor, WDT
Number Of I /o
16
Program Memory Size
8KB (4K x 16)
Program Memory Type
FLASH
Eeprom Size
512 x 8
Ram Size
512 x 8
Voltage - Supply (vcc/vdd)
2.7 V ~ 5.5 V
Data Converters
A/D 11x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 125°C
Package / Case
20-TSSOP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
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18.1.3
18.2
18.2.1
7728G–AVR–06/10
Analog Comparator Inputs
DIDR0 – Digital Input Disable Register 0
Analog Compare Positive Input
Table 18-1.
Note:
• Bits 7,6 – AIN1D, AIN0D: AIN1D and AIN0D Digital Input Disable
When this bit is written logic one, the digital input buffer on the corresponding Analog Com-
pare pin is disabled. The corresponding PIN register bit will always read as zero when this bit
is set. When an analog signal is applied to the AIN0/1 pin and the digital input from this pin is
not needed, this bit should be written logic one to reduce power consumption in the digital
input buffer.
It is possible to select any of the inputs of the ADC Positive Input Multiplexer to replace the
positive input to the Analog Comparator. The ADC multiplexer is used to select this input, and
consequently, the ADC must be switched off to utilize this feature. If the Analog Comparator
Multiplexer Enable bit (ACME in ADCSRB register) is set and the ADC is switched off (ADEN
in ADCSRA register is zero), MUX[4..0] in ADMUX register select the input pin to replace the
positive input to the Analog Comparator, as shown in
is set, AIN1 pin is applied to the positive input to the Analog Comparator.
Bit
Read/Write
Initial Value
ACIS1
0
0
1
1
When changing the ACIS1/ACIS0 bits, the Analog Comparator Interrupt must be disabled by
clearing its Interrupt Enable bit in the ACSR Register. Otherwise an interrupt can occur when
the bits are changed.
ADC7D /
ACIS1 / ACIS0 Settings
AIN1D
R/W
7
0
ACIS0
0
1
0
1
ADC6D /
AIN0D
R/W
6
0
Interrupt Mode
Comparator Interrupt on Output Toggle.
Reserved
Comparator Interrupt on Falling Output Edge.
Comparator Interrupt on Rising Output Edge.
ADC5D
R/W
5
0
ADC4D
R/W
4
0
ADC3D
R/W
3
0
Table
ATtiny87/ATtiny167
ADC2D
18-2. If ACME is cleared or ADEN
R/W
2
0
ADC1D
R/W
1
0
ADC0D
R/W
0
0
DIDR0
213
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