ATTINY87-15SZ Atmel, ATTINY87-15SZ Datasheet - Page 279
![MCU AVR 8K FLASH 15MZ 32-SOIC](/photos/6/80/68042/453-20-soic_sml.jpg)
ATTINY87-15SZ
Manufacturer Part Number
ATTINY87-15SZ
Description
MCU AVR 8K FLASH 15MZ 32-SOIC
Manufacturer
Atmel
Series
AVR® ATtinyr
Datasheet
1.ATTINY167-15MD.pdf
(283 pages)
Specifications of ATTINY87-15SZ
Core Processor
AVR
Core Size
8-Bit
Speed
16MHz
Connectivity
I²C, LIN, SPI, UART/USART, USI
Peripherals
Brown-out Detect/Reset, POR, PWM, Temp Sensor, WDT
Number Of I /o
16
Program Memory Size
8KB (4K x 16)
Program Memory Type
FLASH
Eeprom Size
512 x 8
Ram Size
512 x 8
Voltage - Supply (vcc/vdd)
2.7 V ~ 5.5 V
Data Converters
A/D 11x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 125°C
Package / Case
20-SOIC (7.5mm Width)
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
- Current page: 279 of 283
- Download datasheet (5Mb)
7728G–AVR–06/10
2. Gain control of the crystal oscillator.
The time-out counter is disabled during the RESPONSE when this workaround is set.
The crystal oscillator (0.4 -> 16 MHz) doesn’t latch its gain control (CKSEL/CSEL[2..0]
bits):
a. The ‘Recover System Clock Source’ command doesn’t returns CSEL[2..0] bits.
b. The gain control can be modified on the fly if CLKSELR changes.
Problem fix / workaround .
a. No workaround.
b. As soon as possible, after any CLKSELR modification, re-write the appropriate crystal
Code example:
; (*) !!! Loose gain control of crystal oscillator !!!
; ==> WORKAROUND ...
; ...
; Select crystal oscillator ( 16MHz crystal, fast rising power)
; Enable clock source (crystal oscillator)
;
; Select watchdog clock ( 128KHz, fast rising power)
– Once the RESPONSE is received or sent (having RxOK or TxOK as well as
oscillator setting (CSEL[3]=1 and CSEL[2..0] / CSUT[1..0] bits) in CLKSELR.
Clock source switch
LERR), use the following function:
ldi
sts
ldi
ldi
sts
sts
ldi
sts
sts
ldi
sts
sts
void
}
LINCR = 0x00;
LINBTR = 0x00;
LINCR
lin_wa_tail(void)
temp1,((0x0F<<CSEL0)|(0x02<<CSUT0))
CLKSELR, temp1
temp2,(1<<CLKCCE)
temp3,(0x02<<CLKC0)
CLKCSR,temp2
CLKCSR,temp3
temp3,(0x04<<CLKC0)
CLKCSR,temp2
CLKCSR,temp3
temp3,((0x03<<CSEL0)|(0x02<<CSUT0))
CLKSELR, temp3
CLKSELR, temp1
= (0<<LIN13)|(1<<LENA)|(0<<LCMD2)|(0<<LCMD1)|(0<<LCMD0);
// It is not a RESET !
{
; CSEL = "0010"
; Enable CLKCSR register access
; Enable crystal oscillator clock
; CSEL = "0100"
; Enable CLKCSR register access
; Clock source switch
; (*)
ATtiny87/ATtiny167
279
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