ATTINY87-15SZ Atmel, ATTINY87-15SZ Datasheet - Page 179
![MCU AVR 8K FLASH 15MZ 32-SOIC](/photos/6/80/68042/453-20-soic_sml.jpg)
ATTINY87-15SZ
Manufacturer Part Number
ATTINY87-15SZ
Description
MCU AVR 8K FLASH 15MZ 32-SOIC
Manufacturer
Atmel
Series
AVR® ATtinyr
Datasheet
1.ATTINY167-15MD.pdf
(283 pages)
Specifications of ATTINY87-15SZ
Core Processor
AVR
Core Size
8-Bit
Speed
16MHz
Connectivity
I²C, LIN, SPI, UART/USART, USI
Peripherals
Brown-out Detect/Reset, POR, PWM, Temp Sensor, WDT
Number Of I /o
16
Program Memory Size
8KB (4K x 16)
Program Memory Type
FLASH
Eeprom Size
512 x 8
Ram Size
512 x 8
Voltage - Supply (vcc/vdd)
2.7 V ~ 5.5 V
Data Converters
A/D 11x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 125°C
Package / Case
20-SOIC (7.5mm Width)
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
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15.5.15
15.5.15.1
15.5.15.2
15.5.16
7728G–AVR–06/10
Data Management
OCD Support
LIN FIFO Data Buffer
UART Data Register
The LIN protocol says that a message with an identifier from 60 (0x3C) up to 63 (0x3F) uses a
classic checksum (sum over the data bytes only). Software will be responsible for switching
correctly the LIN13 bit to provide/check this expected checksum (the insertion of the ID field in
the computation of the CRC is set - or not - just after entering the Rx or Tx Response
command).
To preserve register allocation, the LIN data buffer is seen as a FIFO (with address pointer
accessible). This FIFO is accessed via the LINDX[2..0] field of LINSEL register through the
LINDAT register.
LINDX[2..0], the data index, is the address pointer to the required data byte. The data byte can
be read or written. The data index is automatically incremented after each LINDAT access if
the LAINC (active low) bit is cleared. A roll-over is implemented, after data index=7 it is data
index=0. Otherwise, if LAINC bit is set, the data index needs to be written (updated) before
each LINDAT access.
The first byte of a LIN frame is stored at the data index=0, the second one at the data index=1,
and so on. Nevertheless, LINSEL must be initialized by the user before use.
The LINDAT register is the data register (no buffering - no FIFO). In write access, LINDAT will
be for data out and in read access, LINDAT will be for data in.
In UART mode the LINSEL register is unused.
When a debugger break occurs, the state machine of the LIN/UART controller is stopped
(included frame time-out) and further communication may be corrupted.
ATtiny87/ATtiny167
179
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