ATMEGA164P-15MT1 Atmel, ATMEGA164P-15MT1 Datasheet - Page 212

• Manufacturer Part Number: ATMEGA164P-15MT1
• Description: MCU AVR 16K FLASH 15MHZ 44-QFN
• Manufacturer: Atmel
• Series: AVR® ATmegar

Specifications of ATMEGA164P-15MT1

• Core Processor: AVR
• Core Size: 8-Bit
• Speed: 16MHz
• Connectivity: I²C, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, POR, PWM, WDT
• Number Of I /o: 32
• Program Memory Size: 16KB (8K x 16)
• Program Memory Type: FLASH
• Eeprom Size: 512 x 8
• Ram Size: 1K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 5.5 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 105°C
• Package / Case: 44-VQFN
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

19.3.4
212
ATmega164P/324P/644P
Data Packet Format
The MSB of the address byte is transmitted first. Slave addresses can freely be allocated by the
designer, but the address 0000 000 is reserved for a general call.
When a general call is issued, all slaves should respond by pulling the SDA line low in the ACK
cycle. A general call is used when a Master wishes to transmit the same message to several
slaves in the system. When the general call address followed by a Write bit is transmitted on the
bus, all slaves set up to acknowledge the general call will pull the SDA line low in the ack cycle.
The following data packets will then be received by all the slaves that acknowledged the general
call. Note that transmitting the general call address followed by a Read bit is meaningless, as
this would cause contention if several slaves started transmitting different data.
All addresses of the format 1111 xxx should be reserved for future purposes.
Figure 19-4. Address Packet Format
All data packets transmitted on the TWI bus are nine bits long, consisting of one data byte and
an acknowledge bit. During a data transfer, the Master generates the clock and the START and
STOP conditions, while the Receiver is responsible for acknowledging the reception. An
Acknowledge (ACK) is signalled by the Receiver pulling the SDA line low during the ninth SCL
cycle. If the Receiver leaves the SDA line high, a NACK is signalled. When the Receiver has
received the last byte, or for some reason cannot receive any more bytes, it should inform the
Transmitter by sending a NACK after the final byte. The MSB of the data byte is transmitted first.
Figure 19-5. Data Packet Format
Transmitter
Aggregate
SDA from
SDA from
SCL from
SDA
Receiver
SCL
Master
SDA
SLA+R/W
START
Data MSB
Addr MSB
1
1
2
2
Data Byte
7
Addr LSB
Data LSB
8
7
ACK
9
R/W
8
ACK
STOP, REPEATED
9
START or Next
Data Byte
7674F–AVR–09/09