AT91SAM7X128-CU Atmel, AT91SAM7X128-CU Datasheet - Page 675
![no-image](/images/manufacturer_photos/0/0/78/atmel_sml.jpg)
AT91SAM7X128-CU
Manufacturer Part Number
AT91SAM7X128-CU
Description
MCU ARM 128K HS FLASH 100-TFBGA
Manufacturer
Atmel
Series
AT91SAMr
Datasheet
1.AT91SAM7X512-AU-999.pdf
(687 pages)
Specifications of AT91SAM7X128-CU
Core Processor
ARM7
Core Size
16/32-Bit
Speed
55MHz
Connectivity
CAN, Ethernet, I²C, SPI, SSC, UART/USART, USB
Peripherals
Brown-out Detect/Reset, DMA, POR, PWM, WDT
Number Of I /o
62
Program Memory Size
128KB (128K x 8)
Program Memory Type
FLASH
Ram Size
32K x 8
Voltage - Supply (vcc/vdd)
1.65 V ~ 1.95 V
Data Converters
A/D 8x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
100-TFBGA
For Use With
AT91SAM-ICE - EMULATOR FOR AT91 ARM7/ARM9AT91SAM7X-EK - KIT EVAL FOR AT91SAM7X256/128
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Part Number:
AT91SAM7X128-CU
Manufacturer:
ATMEL/爱特梅尔
Quantity:
20 000
- Current page: 675 of 687
- Download datasheet (11Mb)
6120H–ATARM–17-Feb-09
Version
6120F
(Continued) Comments
PIO:Section 27.4.4 “Output Control” on page
Section 27.4.1 “Pull-up Resistor Control” on page 233
Figure 27-3 on page 232
SPI:
location defined.
Section 28.7.4 “SPI Transmit Data Register” on page
Section 28.7.2 “SPI Mode Register” on page
Updated
“SPI Mode Register” on page 269
description modified in
Updated
Updated information on SPI_RDR in
information to SWRST bit description in
equations in DLYBCT bit description,
Changes to
USART:
Manchester Functionality Removed.
Section 30.4 “I/O Lines Description” on page
Section 30.6.1.3 “Fractional Baud Rate in Asynchronous Mode” on page
mode” changed to USART “normal mode”.
Table 30-3, “Binary and Decimal Values for Di,” on page 311
for Fi,” on page
Figure 30-25, ”IrDA Demodulator Operations” on page 327
Section 30.6.4.1 “ISO7816 Mode Overview” on page 323
Section 30.6.7 “Modem Mode” on page 329
Table 30-2, “Baud Rate Example (OVER = 0),” on page 308
“Asynchronous Receiver” on page 313
“Receiver Time-out” on page 318
Section 30.7.1 ”USART Control Register”
Section 30.7.6 ”USART Channel Status Register”
TC:
used as an output and the compare register B is not used to generate waveforms and subsequently no
IRQs. Note
Waveform Mode” on page 411
PWM:
Section 34. “USB Device Port (UDP)” on page
throughout section, new source document.
Section 34.5.3.8 ”Sending a Device Remote Wakeup”
WAKEUP bit shown in interruput registers:
RMWUPE, RSMINPR, ESR bits removed from
NOTE: pertinent to USB pullup effect on USB Reset added to
Register”.
Section 32.5.12 “External Event/Trigger Conditions” on page 404
Section 28.7.5 “SPI Status Register” on page 273
Section 33.5.3.3 ”Changing the Duty Cycle or the
Figure 28-1, ”Block Diagram” on page
Figure 28-9, ”Slave Mode Functional Block Diagram” on page 266
(1)
Section 28.6.3.8 “Mode Fault Detection” on page
attached to ”EEVT: External Event Selection” in
311: DI and Fi properly referenced in titles.
Section 28.7.2 “SPI Mode Register” on page
0 and 1 inverted in the MUX controlled by PIO_MDSR..
further clarifies this condition.
list of user options rewritten.
and
Section 28.6.3 “Master Mode Operations” on page
Section 28.7.9 ”SPI Chip Select Register”
Section 28.7.9 “SPI Chip Select Register” on page
2nd line in 4th paragraph changed.
Section 28.7.1 “SPI Control Register” on page
STTTO bit function related to TIMEOUT in US_CSR register
AT91SAM7X512/256/128 Preliminary
Section 34.6.4 on page 470
Control of DTR and RTS output pins.
269,
305, text concerning TXD line added.
233, typo corrected
441: Corrections, improvements, additions and deletions
Section 34.6.2 ”UDP Global State Register”
256, removed Note. Removed bit FDIV from
TIMEOUT bit function related to STTO in US_CR register
PCSDEC: Chip Select Decode
272,
reference to resistor value removed.
replaces title “Sending an External Resume.
SPI_RCR, SPI_RNCR, SPI_TCR, SPI_TNCR
Period”: updated info on waveform generation.
clarification of PAR configuration added.
LASTXFER: Last Transfer
modified.
60k and 70k MHz clock speeds removed.
and
265.
Section 34.6.12 ”UDP Transceiver Control
Section 32.6.5 “TC Channel Mode Register:
Table 30-4, “Binary and Decimal Values
269.
“....(EEVT = 0), TIOB is no longer
thru
309, using USART “functional
to remove FLOAD.
Section 34.6.8 on page 476
on
changed.
page
text added.
268. Corrected
260. Added
279.
278. LLB
Section 28.7.2
Change
Request
Ref.
05-346
05-497
3053
04-183
05-434
05-476
05-484
1542
1543
1676
2768
1552
1770
2942
3023
2704
1677
3288
675
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