AT91SAM7X128-CU Atmel, AT91SAM7X128-CU Datasheet - Page 652
AT91SAM7X128-CU
Manufacturer Part Number
AT91SAM7X128-CU
Description
MCU ARM 128K HS FLASH 100-TFBGA
Manufacturer
Atmel
Series
AT91SAMr
Datasheet
1.AT91SAM7X512-AU-999.pdf
(687 pages)
Specifications of AT91SAM7X128-CU
Core Processor
ARM7
Core Size
16/32-Bit
Speed
55MHz
Connectivity
CAN, Ethernet, I²C, SPI, SSC, UART/USART, USB
Peripherals
Brown-out Detect/Reset, DMA, POR, PWM, WDT
Number Of I /o
62
Program Memory Size
128KB (128K x 8)
Program Memory Type
FLASH
Ram Size
32K x 8
Voltage - Supply (vcc/vdd)
1.65 V ~ 1.95 V
Data Converters
A/D 8x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
100-TFBGA
For Use With
AT91SAM-ICE - EMULATOR FOR AT91 ARM7/ARM9AT91SAM7X-EK - KIT EVAL FOR AT91SAM7X256/128
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Part Number:
AT91SAM7X128-CU
Manufacturer:
ATMEL/爱特梅尔
Quantity:
20 000
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41.3.2
41.3.2.1
41.3.2.2
41.3.3
41.3.3.1
41.3.4
41.3.4.1
41.3.4.2
652
AT91SAM7X512/256/128 Preliminary
Controller Area Network (CAN)
Embedded Flash Controller (EFC)
Ethernet MAC (EMAC)
CAN: Low Power Mode and Error Frame
CAN: Low Power Mode and Pending Transmit Messages
EFC: Embedded Flash Access Time
EMAC: Possible Event Loss when Reading EMAC_ISR
EMAC: Possible Event Loss when Reading the Statistics Register Block
If the Low Power Mode is activated while the CAN is generating an error frame, this error frame
may be shortened.
None
No pending transmit messages may be sent once the CAN Controller enters Low-power Mode.
Check that all messages have been sent by reading the related Flags before entering Low-
power Mode.
The embedded Flash maximum access time is 25 MHz (instead of 30 MHz at zero Wait State
(FWS = 0). The maximum operating frequency with one Wait State (FWS = 1) is still 55 MHz.
Set one wait state (FWS = 1) if the temperature is above 25 MHz.
If an event occurs within the same clock cycle in which the EMAC_ISR is read, the correspond-
ing bit might be cleared even though it has not been read at 1. This might lead to the loss of this
event.
Each time the software reads EMAC_ISR, it has to check the contents of the Transmit Status
Register (EMAC_TSR), the Receive Status Register (EMAC_RSR) and the Network Status
Register (EMAC_NSR), as the possible lost event is still notified in one of these registers.
If an event occurs within the same clock cycle during which a statistics register is read, the cor-
responding counter might lose this event. This might lead to the loss of the incrementation of
one for this counter.
None
Problem Fix/Workaround
Problem Fix/Workaround
Problem Fix/Workaround
Problem Fix/Workaround
Problem Fix/Workaround
6120H–ATARM–17-Feb-09
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