AT91R40807-33AU Atmel, AT91R40807-33AU Datasheet - Page 11

• Manufacturer Part Number: AT91R40807-33AU
• Description: IC ARM7 MCU 100TQFP
• Manufacturer: Atmel
• Series: AT91SAMr

Specifications of AT91R40807-33AU

• Core Processor: ARM7
• Core Size: 16/32-Bit
• Speed: 33MHz
• Connectivity: EBI/EMI, UART/USART
• Peripherals: WDT
• Number Of I /o: 32
• Program Memory Type: ROMless
• Ram Size: 136K x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 3.6 V
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 100-TQFP, 100-VQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Data Converters: -

Peripherals
Peripheral Registers
Peripheral Interrupt Control
Peripheral Data Controller
1345DS–ATARM–02/02
The AT91R40807 peripherals are connected to the 32-bit wide Advanced Peripheral
Bus. Peripheral registers are only word accessible
not supported. If a byte or a half-word access is attempted, the memory controller auto-
matically masks the lowest address bits and generates an word access.
Each peripheral has a 16-Kbyte address space allocated (the AIC only has a 4-Kbyte
address space).
The following registers are common to all peripherals:
•
•
•
•
•
Unused bits in the peripheral registers are shown as “
upward compatibility. These bits read 0.
The Interrupt Control of each peripheral is controlled from the status register using the
interrupt mask. The status register bits are ANDed to their corresponding interrupt mask
bits and the result is then ORed to generate the Interrupt Source signal to the Advanced
Interrupt Controller.
The interrupt mask is read in the Interrupt Mask Register and is modified with the Inter-
rupt Enable Register and the Interrupt Disable Register. The enable/disable/status (or
mask) makes it possible to enable or disable peripheral interrupt sources with a non-
interruptible single instruction. This eliminates the need for interrupt masking at the AIC
or core level in real-time and multi-tasking systems.
The AT91R40807 microcontroller has a 4-channel PDC dedicated to the two on-chip
USARTs. One PDC channel is dedicated to the receiver and one to the transmitter of
each USART.
The user interface of a PDC channel is integrated in the memory space of each USART.
It contains a 32-bit Address Pointer Register (RPR or TPR) and a 16-bit Transfer
Counter Register (RCR or TCR). When the programmed number of transfers are per-
formed, a status bit indicating the end of transfer is set in the USART Status Register
and an interrupt can be generated.
Control Register
to the corresponding position at the appropriate address. Writing a zero has no
effect.
Mode Register
Usually has a value of 0x0 after a reset.
Data Registers
between the processor and the peripheral.
Status Register
Enable/Disable/Status Registers
Enable Register sets the corresponding bit in the Status Register. Writing a one in
the Disable Register resets the corresponding bit and the result can be read in the
Status Register. Writing a bit to zero has no effect. This register access method
maximizes the efficiency of bit manipulation, and enables modification of a register
with a single non-interruptible instruction, replacing the costly read-modify-write
operation.
–
–
–
–
read/write register that defines the configuration of the peripheral.
read and/or write register that enables the exchange of data
read only register that returns the status of the peripheral.
write only register that triggers a command when a one is written
–
shadow command registers. Writing a one in the
–
byte and half-word accesses are
–
” and must be written at 0 for
AT91R40807
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