DSPIC30F4013T-20I/ML Microchip Technology, DSPIC30F4013T-20I/ML Datasheet - Page 61

• Manufacturer Part Number: DSPIC30F4013T-20I/ML
• Description: IC DSPIC MCU/DSP 48K 44QFN
• Manufacturer: Microchip Technology
• Series: dsPIC™ 30Fr

Specifications of DSPIC30F4013T-20I/ML

• Core Processor: dsPIC
• Core Size: 16-Bit
• Speed: 20 MIPS
• Connectivity: CAN, I²C, SPI, UART/USART
• Peripherals: AC'97, Brown-out Detect/Reset, I²S, POR, PWM, WDT
• Number Of I /o: 30
• Program Memory Size: 48KB (16K x 24)
• Program Memory Type: FLASH
• Eeprom Size: 1K x 8
• Ram Size: 2K x 8
• Voltage - Supply (vcc/vdd): 2.5 V ~ 5.5 V
• Data Converters: A/D 13x12b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 44-QFN
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Other names: DSPIC30F4013T20IM

Each hard trap that occurs must be acknowledged
before code execution of any type may continue. If a
lower priority hard trap occurs while a higher priority
trap is pending, acknowledged, or is being processed,
a hard trap conflict will occur.
The device is automatically Reset in a hard trap conflict
condition. The TRAPR status bit (RCON<15>) is set
when the Reset occurs, so that the condition may be
detected in software.
FIGURE 8-1:
8.4
All interrupt event flags are sampled in the beginning of
each instruction cycle by the IFSx registers. A pending
interrupt request (IRQ) is indicated by the flag bit being
equal to a ‘1’ in an IFSx register. The IRQ will cause an
interrupt to occur if the corresponding bit in the Interrupt
Enable (IECx) register is set. For the remainder of the
instruction cycle, the priorities of all pending interrupt
requests are evaluated.
If there is a pending IRQ with a priority level greater
than the current processor priority level in the IPL bits,
the processor will be interrupted.
The processor then stacks the current program counter
and the low byte of the processor STATUS register
(SRL), as shown in Figure 8-2. The low byte of the
STATUS register contains the processor priority level at
the time prior to the beginning of the interrupt cycle.
The processor then loads the priority level for this inter-
 2004 Microchip Technology Inc.
AIVT
Interrupt Sequence
IVT
Oscillator Fail Trap Vector
Address Error Trap Vector
Oscillator Fail Trap Vector
Address Error Trap Vector
Reset - GOTO Instruction
Stack Error Trap Vector
Stack Error Trap Vector
Math Error Trap Vector
Math Error Trap Vector
Reset - GOTO Address
Interrupt 52 Vector
Interrupt 53 Vector
Interrupt 52 Vector
Interrupt 53 Vector
Interrupt 0 Vector
Interrupt 1 Vector
Interrupt 0 Vector
Interrupt 1 Vector
Reserved Vector
Reserved Vector
Reserved Vector
Reserved Vector
Reserved Vector
Reserved Vector
TRAP VECTORS
Reserved
Reserved
Reserved
Reserved
—
—
—
—
—
—
0x000000
0x000014
0x000094
0x0000FE
0x000002
0x000004
0x00007E
0x000082
0x000084
0x000080
Advance Information
rupt into the STATUS register. This action will disable
all lower priority interrupts until the completion of the
Interrupt Service Routine.
FIGURE 8-2:
The RETFIE (return from interrupt) instruction will
unstack the program counter and STATUS registers to
return the processor to its state prior to the interrupt
sequence.
8.5
In program memory, the Interrupt Vector Table (IVT) is
followed by the Alternate Interrupt Vector Table (AIVT),
as shown in Figure 8-1. Access to the alternate vector
table is provided by the ALTIVT bit in the INTCON2 reg-
ister. If the ALTIVT bit is set, all interrupt and exception
processes will use the alternate vectors instead of the
default vectors. The alternate vectors are organized in
the same manner as the default vectors. The AIVT sup-
ports emulation and debugging efforts by providing a
means to switch between an application and a support
environment without requiring the interrupt vectors to
be reprogrammed. This feature also enables switching
between applications for evaluation of different
software algorithms at run time.
If the AIVT is not required, the program memory allo-
cated to the AIVT may be used for other purposes.
AIVT is not a protected section and may be freely
programmed by the user.
0x0000
dsPIC30F3014/4013
Note 1: The user can always lower the priority
2: The IPL3 bit (CORCON<3>) is always
Alternate Vector Table
SRL IPL3 PC<22:16>
15
level by writing a new value into SR. The
Interrupt Service Routine must clear the
interrupt flag bits in the IFSx register
before lowering the processor interrupt
priority, in order to avoid recursive
interrupts.
clear when interrupts are being pro-
cessed. It is set only during execution of
traps.
<Free Word>
PC<15:0>
INTERRUPT STACK FRAME
0
POP : [--W15]
PUSH: [W15++]
W15 (before CALL)
W15 (after CALL)
DS70138C-page 59