DSPIC30F4013T-20I/ML Microchip Technology, DSPIC30F4013T-20I/ML Datasheet - Page 212

• Manufacturer Part Number: DSPIC30F4013T-20I/ML
• Description: IC DSPIC MCU/DSP 48K 44QFN
• Manufacturer: Microchip Technology
• Series: dsPIC™ 30Fr

Specifications of DSPIC30F4013T-20I/ML

• Core Processor: dsPIC
• Core Size: 16-Bit
• Speed: 20 MIPS
• Connectivity: CAN, I²C, SPI, UART/USART
• Peripherals: AC'97, Brown-out Detect/Reset, I²S, POR, PWM, WDT
• Number Of I /o: 30
• Program Memory Size: 48KB (16K x 24)
• Program Memory Type: FLASH
• Eeprom Size: 1K x 8
• Ram Size: 2K x 8
• Voltage - Supply (vcc/vdd): 2.5 V ~ 5.5 V
• Data Converters: A/D 13x12b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 44-QFN
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Other names: DSPIC30F4013T20IM

dsPIC30F3014/4013
Data Address Space ........................................................... 28
Data Converter Interface (DCI) Module ............................ 115
Data EEPROM Memory ...................................................... 47
DC Characteristics ............................................................ 163
DCI Module
DS70138C-page 210
Alignment .................................................................... 31
Alignment (Figure) ...................................................... 31
Effect of Invalid Memory Accesses (Table)................. 31
MCU and DSP (MAC Class) Instructions Example..... 30
Memory Map ......................................................... 28, 29
Near Data Space ........................................................ 32
Software Stack ............................................................ 32
Spaces ........................................................................ 31
Width........................................................................... 31
Erasing ........................................................................ 48
Erasing, Block ............................................................. 48
Erasing, Word ............................................................. 48
Protection Against Spurious Write .............................. 50
Reading....................................................................... 47
Write Verify ................................................................. 50
Writing ......................................................................... 49
Writing, Block .............................................................. 49
Writing, Word .............................................................. 49
BOR .......................................................................... 174
Brown-out Reset ....................................................... 173
I/O Pin Input Specifications ....................................... 171
I/O Pin Output Specifications .................................... 172
Idle Current (I
Low-Voltage Detect................................................... 172
LVDL ......................................................................... 173
Operating Current (I
Power-Down Current (I
Program and EEPROM............................................. 174
Temperature and Voltage Specifications .................. 163
Bit Clock Generator................................................... 119
Buffer Alignment with Data Frames .......................... 121
Buffer Control ............................................................ 115
Buffer Data Alignment ............................................... 115
Buffer Length Control................................................ 121
COFS Pin.................................................................. 115
CSCK Pin.................................................................. 115
CSDI Pin ................................................................... 115
CSDO Mode Bit ........................................................ 122
CSDO Pin ................................................................. 115
Data Justification Control Bit ..................................... 120
Device Frequencies for Common Codec CSCK Frequen-
Digital Loopback Mode ............................................. 122
Enable....................................................................... 117
Frame Sync Generator ............................................. 117
Frame Sync Mode Control Bits ................................. 117
I/O Pins ..................................................................... 115
Interrupts ................................................................... 122
Introduction ............................................................... 115
Master Frame Sync Operation .................................. 117
Operation .................................................................. 117
Operation During CPU Idle Mode ............................. 122
Operation During CPU Sleep Mode .......................... 122
Receive Slot Enable Bits........................................... 120
Receive Status Bits ................................................... 121
Register Map............................................................. 124
Sample Clock Edge Control Bit................................. 120
Slave Frame Sync Operation .................................... 118
Slot Enable Bits Operation with Frame Sync ............ 120
Slot Status Bits.......................................................... 122
cies (Table) ....................................................... 119
IDLE
) .................................................... 167
DD
)............................................. 165
PD
) ........................................ 169
Advance Information
Demonstration Boards
Development Support ....................................................... 157
Device Configuration
Device Configuration Registers
Device Overview................................................................... 9
Disabling the UART ............................................................ 99
Divide Support .................................................................... 16
DSP Engine ........................................................................ 17
Dual Output Compare Match Mode .................................... 82
E
Electrical Characteristics .................................................. 163
Enabling and Setting Up UART
Enabling the UART ............................................................. 99
Equations
Errata .................................................................................... 7
Evaluation and Programming Tools.................................. 161
Exception Sequence
External Clock Timing Characteristics
External Clock Timing Requirements ............................... 176
External Interrupt Requests ................................................ 60
Synchronous Data Transfers .................................... 120
Timing Characteristics
Timing Requirements
Transmit Slot Enable Bits ......................................... 120
Transmit Status Bits.................................................. 121
Transmit/Receive Shift Register ............................... 115
Underflow Mode Control Bit...................................... 122
Word Size Selection Bits .......................................... 117
PICDEM 1................................................................. 160
PICDEM 17............................................................... 160
PICDEM 18R ............................................................ 161
PICDEM 2 Plus......................................................... 160
PICDEM 3................................................................. 160
PICDEM 4................................................................. 160
PICDEM LIN ............................................................. 161
PICDEM USB ........................................................... 161
PICDEM.net Internet/Ethernet .................................. 160
Register Map ............................................................ 148
FBORPOR ................................................................ 146
FGS .......................................................................... 146
FOSC........................................................................ 146
FWDT ....................................................................... 146
Instructions (Table) ..................................................... 16
Multiplier ..................................................................... 19
Continuous Pulse Mode.............................................. 82
Single Pulse Mode...................................................... 82
AC............................................................................. 175
DC ............................................................................ 163
Alternate I/O ............................................................... 99
Setting Up Data, Parity and Stop Bit Selections ......... 99
A/D Conversion Clock............................................... 127
Baud Rate................................................................. 101
Bit Clock Frequency.................................................. 119
COFSG Period.......................................................... 117
Serial Clock Rate ........................................................ 94
Time Quantum for Clock Generation ........................ 111
Trap Sources .............................................................. 58
Type A, B and C Timer ............................................. 183
Type A Timer ............................................................ 183
Type B Timer ............................................................ 184
Type C Timer ............................................................ 184
AC-Link Mode................................................... 189
Multichannel, I
AC-Link Mode................................................... 189
Multichannel, I
2
2
S Modes................................... 187
S Modes................................... 188
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