PIC18F4580T-I/ML Microchip Technology, PIC18F4580T-I/ML Datasheet - Page 412

IC PIC MCU FLASH 16KX16 44QFN

PIC18F4580T-I/ML

Manufacturer Part Number
PIC18F4580T-I/ML
Description
IC PIC MCU FLASH 16KX16 44QFN
Manufacturer
Microchip Technology
Series
PIC® 18Fr

Specifications of PIC18F4580T-I/ML

Core Processor
PIC
Core Size
8-Bit
Speed
40MHz
Connectivity
CAN, I²C, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, HLVD, POR, PWM, WDT
Number Of I /o
36
Program Memory Size
32KB (16K x 16)
Program Memory Type
FLASH
Eeprom Size
256 x 8
Ram Size
1.5K x 8
Voltage - Supply (vcc/vdd)
4.2 V ~ 5.5 V
Data Converters
A/D 11x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
44-QFN
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
PIC18F2480/2580/4480/4580
MOVSS
Syntax:
Operands:
Operation:
Status Affected:
Encoding:
1st word (source)
2nd word (dest.)
Description
Words:
Cycles:
Example:
DS39637D-page 412
Q Cycle Activity:
Before Instruction
After Instruction
Decode
Decode
FSR2
Contents
of 85h
Contents
of 86h
FSR2
Contents
of 85h
Contents
of 86h
Q1
source addr
Determine
Determine
dest addr
Move Indexed to Indexed
MOVSS [z
0 ≤ z
0 ≤ z
((FSR2) + z
None
The contents of the source register are
moved to the destination register. The
addresses of the source and destination
registers are determined by adding the
7-bit literal offsets ‘z
respectively, to the value of FSR2. Both
registers can be located anywhere in
the 4096-byte data memory space
(000h to FFFh).
The MOVSS instruction cannot use the
PCL, TOSU, TOSH or TOSL as the
destination register.
If the resultant source address points to
an indirect addressing register, the
value returned will be 00h. If the
resultant destination address points to
an indirect addressing register, the
instruction will execute as a NOP.
2
2
MOVSS [05h], [06h]
1110
1111
Q2
=
=
=
=
=
=
s
d
≤ 127
≤ 127
80h
33h
11h
80h
33h
33h
s
s
source addr
1011
xxxx
], [z
) → ((FSR2) + z
Determine
Determine
dest addr
d
Q3
]
s
’ or ‘z
1zzz
xzzz
d
source reg
to dest reg
’,
d
)
Read
Write
Q4
zzzz
zzzz
s
d
PUSHL
Syntax:
Operands:
Operation:
Status Affected: None
Encoding:
Description:
Words:
Cycles:
Example:
Q Cycle Activity:
Before Instruction
After Instruction
Decode
FSR2H:FSR2L
Memory (01ECh)
FSR2H:FSR2L
Memory (01ECh)
Q1
Store Literal at FSR2, Decrement FSR2
PUSHL k
0 ≤ k ≤ 255
k → (FSR2),
FSR2 – 1→ FSR2
The 8-bit literal ‘k’ is written to the data
memory address specified by FSR2. FSR2 is
decremented by 1 after the operation.
This instruction allows users to push values
onto a software stack.
1
1
1111
Read ‘k’
PUSHL 08h
Q2
© 2009 Microchip Technology Inc.
1010
=
=
=
=
Process
data
Q3
01ECh
01EBh
00h
08h
kkkk
destination
Write to
kkkk
Q4

Related parts for PIC18F4580T-I/ML