PIC18F4580T-I/ML Microchip Technology, PIC18F4580T-I/ML Datasheet - Page 179

• Manufacturer Part Number: PIC18F4580T-I/ML
• Description: IC PIC MCU FLASH 16KX16 44QFN
• Manufacturer: Microchip Technology
• Series: PIC® 18Fr

Specifications of PIC18F4580T-I/ML

• Core Processor: PIC
• Core Size: 8-Bit
• Speed: 40MHz
• Connectivity: CAN, I²C, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, HLVD, POR, PWM, WDT
• Number Of I /o: 36
• Program Memory Size: 32KB (16K x 16)
• Program Memory Type: FLASH
• Eeprom Size: 256 x 8
• Ram Size: 1.5K x 8
• Voltage - Supply (vcc/vdd): 4.2 V ~ 5.5 V
• Data Converters: A/D 11x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 44-QFN
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant

17.4
The Enhanced PWM mode provides additional PWM
output options for a broader range of control applica-
tions. The module is a backward compatible version of
the standard CCP module and offers up to four outputs,
designated P1A through P1D. Users are also able to
select the polarity of the signal (either active-high or
active-low). The module’s output mode and polarity are
configured by setting the
CCP1M<3:0> bits of the ECCP1CON register.
Figure 17-1 shows a simplified block diagram of PWM
operation. All control registers are double-buffered and
are loaded at the beginning of a new PWM cycle (the
period boundary when Timer2 resets) in order to
prevent glitches on any of the outputs. The exception is
the
ECCP1DEL, which is loaded at either the duty cycle
boundary or the boundary period (whichever comes
first). Because of the buffering, the module waits until
the assigned timer resets instead of starting immedi-
ately. This means that Enhanced PWM waveforms do
not exactly match the standard PWM waveforms, but
are instead offset by one full instruction cycle (4 T
As before, the user must manually configure the
appropriate TRIS bits for output.
FIGURE 17-1:
© 2009 Microchip Technology Inc.
ECCP
Enhanced PWM Mode
Note: The 8-bit TMR2 register is concatenated with the 2-bit internal Q clock, or 2 bits of the prescaler, to create the 10-bit time
ECCPR1H (Slave)
Duty Cycle Registers
Comparator
PWM
ECCPR1L
PR2
base.
TMR2
Comparator
SIMPLIFIED BLOCK DIAGRAM OF THE ENHANCED PWM MODULE
Dead-Band
(Note 1)
Clear Timer,
set ECCP1 pin and
latch D.C.
CCP1CON<5:4>
EPWM1M<1:0> and
Delay
R
S
PIC18F2480/2580/4480/4580
register,
OSC
EPWM1M1<1:0>
Q
).
ECCP1DEL
Controller
ECCP1/P1A
Output
17.4.1
The PWM period is specified by writing to the PR2
register. The PWM period can be calculated using the
following equation.
EQUATION 17-1:
PWM frequency is defined as 1/[PWM period]. When
TMR2 is equal to PR2, the following three events occur
on the next increment cycle:
• TMR2 is cleared
• The ECCP1 pin is set (if PWM duty cycle = 0%,
• The PWM duty cycle is copied from ECCPR1L
2
the ECCP1 pin will not be set)
into ECCPR1H
Note:
P1C
P1D
P1B
PWM Period =
4
CCP1M<3:0>
PWM PERIOD
The Timer2 postscaler (see Section 14.0
“Timer2 Module”) is not used in the
determination of the PWM frequency. The
postscaler could be used to have a servo
update rate at a different frequency than
the PWM output.
TRISD<4>
TRISD<5>
TRISD<6>
TRISD<7>
[(PR2) + 1] • 4 • T
(TMR2 Prescale Value)
ECCP1/P1A
P1B
P1C
P1D
DS39637D-page 179
OSC
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