PIC18F4580T-I/ML Microchip Technology, PIC18F4580T-I/ML Datasheet - Page 256

• Manufacturer Part Number: PIC18F4580T-I/ML
• Description: IC PIC MCU FLASH 16KX16 44QFN
• Manufacturer: Microchip Technology
• Series: PIC® 18Fr

Specifications of PIC18F4580T-I/ML

• Core Processor: PIC
• Core Size: 8-Bit
• Speed: 40MHz
• Connectivity: CAN, I²C, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, HLVD, POR, PWM, WDT
• Number Of I /o: 36
• Program Memory Size: 32KB (16K x 16)
• Program Memory Type: FLASH
• Eeprom Size: 256 x 8
• Ram Size: 1.5K x 8
• Voltage - Supply (vcc/vdd): 4.2 V ~ 5.5 V
• Data Converters: A/D 11x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 44-QFN
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant

PIC18F2480/2580/4480/4580
The analog reference voltage is software-selectable to
either the device’s positive and negative supply voltage
(AV
RA3/AN3/V
The A/D Converter has a unique feature of being able
to operate while the device is in Sleep mode. To oper-
ate in Sleep, the A/D conversion clock must be derived
from the A/D’s internal RC oscillator.
The output of the sample and hold is the input into the
converter, which generates the result via successive
approximation.
FIGURE 20-1:
DS39637D-page 256
DD
Note 1:
and AV
REF
2:
+ and RA2/AN2/V
Converter
SS
10-Bit
Channels, AN5 through AN7, are not available on PIC18F2X80 devices.
I/O pins have diode protection to V
), or the voltage level on the
A/D
Reference
Voltage
A/D BLOCK DIAGRAM
REF
-/CV
V
V
REF
REF
REF
+
-
pins.
(Input Voltage)
VCFG<1:0>
V
AIN
DD
and V
X
X
1
0
AV
0
1
X
X
SS
DD
A device Reset forces all registers to their Reset state.
This forces the A/D module to be turned off and any
conversion in progress is aborted.
Each port pin associated with the A/D Converter can be
configured as an analog input, or as a digital I/O. The
ADRESH and ADRESL registers contain the result of
the A/D conversion. When the A/D conversion is com-
plete, the result is loaded into the ADRESH/ADRESL
registers, the GO/DONE bit (ADCON0 register) is
cleared and A/D Interrupt Flag bit, ADIF, is set. The
block diagram of the A/D module is shown in
Figure 20-1.
.
(2)
AV
SS
(2)
CHS<3:0>
1010
1001
1000
0111
0110
0101
0100
0011
0010
0001
0000
© 2009 Microchip Technology Inc.
AN10
AN9
AN8
AN7
AN6
AN5
AN4
AN3
AN2
AN1
AN0
(1)
(1)
(1)