ATMEGA329-16MI Atmel, ATMEGA329-16MI Datasheet - Page 96
![IC AVR MCU 32K 16MHZ 64-QFN](/photos/12/13/121326/313-64-qfn_sml.jpg)
ATMEGA329-16MI
Manufacturer Part Number
ATMEGA329-16MI
Description
IC AVR MCU 32K 16MHZ 64-QFN
Manufacturer
Atmel
Series
AVR® ATmegar
Specifications of ATMEGA329-16MI
Core Processor
AVR
Core Size
8-Bit
Speed
16MHz
Connectivity
SPI, UART/USART, USI
Peripherals
Brown-out Detect/Reset, LCD, POR, PWM, WDT
Number Of I /o
54
Program Memory Size
32KB (16K x 16)
Program Memory Type
FLASH
Eeprom Size
1K x 8
Ram Size
2K x 8
Voltage - Supply (vcc/vdd)
2.7 V ~ 5.5 V
Data Converters
A/D 8x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
64-MLF®, 64-QFN
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
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14.6.1
96
ATmega329/3290/649/6490
Compare Output Mode and Waveform Generation
Figure 14-4. Compare Match Output Unit, Schematic
The general I/O port function is overridden by the Output Compare (OC0A) from the Waveform
Generator if either of the COM0A1:0 bits are set. However, the OC0A pin direction (input or out-
put) is still controlled by the Data Direction Register (DDR) for the port pin. The Data Direction
Register bit for the OC0A pin (DDR_OC0A) must be set as output before the OC0A value is vis-
ible on the pin. The port override function is independent of the Waveform Generation mode.
The design of the Output Compare pin logic allows initialization of the OC0A state before the
output is enabled. Note that some COM0A1:0 bit settings are reserved for certain modes of
operation.
The Waveform Generator uses the COM0A1:0 bits differently in Normal, CTC, and PWM
modes. For all modes, setting the COM0A1:0 = 0 tells the Waveform Generator that no action on
the OC0A Register is to be performed on the next compare match. For compare output actions
in the non-PWM modes refer to
4 on page
A change of the COM0A1:0 bits state will have effect at the first compare match after the bits are
written. For non-PWM modes, the action can be forced to have immediate effect by using the
FOC0A strobe bits.
See “Register Description” on page 103.
104, and for phase correct PWM refer to
COMnx1
COMnx0
FOCn
clk
I/O
Waveform
Generator
Table 14-3 on page
D
D
D
PORT
DDR
OCnx
Q
Q
Q
Table 14-5 on page
104. For fast PWM mode, refer to
1
0
105.
OCn
Pin
2552K–AVR–04/11
Table 14-
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