ATMEGA329-16MI Atmel, ATMEGA329-16MI Datasheet - Page 76
![IC AVR MCU 32K 16MHZ 64-QFN](/photos/12/13/121326/313-64-qfn_sml.jpg)
ATMEGA329-16MI
Manufacturer Part Number
ATMEGA329-16MI
Description
IC AVR MCU 32K 16MHZ 64-QFN
Manufacturer
Atmel
Series
AVR® ATmegar
Specifications of ATMEGA329-16MI
Core Processor
AVR
Core Size
8-Bit
Speed
16MHz
Connectivity
SPI, UART/USART, USI
Peripherals
Brown-out Detect/Reset, LCD, POR, PWM, WDT
Number Of I /o
54
Program Memory Size
32KB (16K x 16)
Program Memory Type
FLASH
Eeprom Size
1K x 8
Ram Size
2K x 8
Voltage - Supply (vcc/vdd)
2.7 V ~ 5.5 V
Data Converters
A/D 8x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
64-MLF®, 64-QFN
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
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ATmega329/3290/649/6490
• XCK/AIN0/PCINT2 – Port E, Bit 2
XCK, USART0 External Clock. The Data Direction Register (DDE2) controls whether the clock is
output (DDE2 set) or input (DDE2 cleared). The XCK pin is active only when the USART0 oper-
ates in synchronous mode.
AIN0 – Analog Comparator Positive input. This pin is directly connected to the positive input of
the Analog Comparator.
PCINT2, Pin Change Interrupt Source 2: The PE2 pin can serve as an external interrupt source.
• TXD/PCINT1 – Port E, Bit 1
TXD0, UART0 Transmit pin.
PCINT1, Pin Change Interrupt Source 1: The PE1 pin can serve as an external interrupt source.
• RXD/PCINT0 – Port E, Bit 0
RXD, USART0 Receive pin. Receive Data (Data input pin for the USART0). When the USART0
Receiver is enabled this pin is configured as an input regardless of the value of DDE0. When the
USART0 forces this pin to be an input, a logical one in PORTE0 will turn on the internal pull-up.
PCINT0, Pin Change Interrupt Source 0: The PE0 pin can serve as an external interrupt source.
Table 13-16
shown in
Table 13-16. Overriding Signals for Alternate Functions PE7:PE4
Note:
Signal
Name
PUOE
PUOV
DDOE
DDOV
PVOE
PVOV
PTOE
DIEOE
DIEOV
DI
AIO
1. CKOUT is one if the CKOUT Fuse is programmed
Figure 13-5 on page
and
PE7/PCINT7
0
0
CKOUT
1
CKOUT
clk
–
PCINT7 • PCIE0
1
PCINT7 INPUT
–
Table 13-17
I/O
(1)
(1)
relates the alternate functions of Port E to the overriding signals
65.
PE6/DO/
PCINT6
0
0
0
0
USI_THREE-
WIRE
DO
–
PCINT6 • PCIE0
1
PCINT6 INPUT
–
PE5/DI/SDA/
PCINT5
USI_TWO-WIRE
0
USI_TWO-WIRE
(SDA +
PORTE5) •
DDE5
USI_TWO-WIRE
• DDE5
0
0
(PCINT5 •
PCIE0) + USISIE
1
DI/SDA INPUT
PCINT5 INPUT
–
PE4/USCK/SCL/
PCINT4
0
(USI_SCL_HOL
D + PORTE4) •
DDE4
USI_TWO-WIRE
• DDE4
0
USITC
(PCINT4 •
PCIE0) + USISIE
1
USCKL/SCL
INPUT
PCINT4 INPUT
–
USI_TWO-WIRE
USI_TWO-WIRE
2552K–AVR–04/11
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