ATMEGA329-16MI Atmel, ATMEGA329-16MI Datasheet - Page 22
![IC AVR MCU 32K 16MHZ 64-QFN](/photos/12/13/121326/313-64-qfn_sml.jpg)
ATMEGA329-16MI
Manufacturer Part Number
ATMEGA329-16MI
Description
IC AVR MCU 32K 16MHZ 64-QFN
Manufacturer
Atmel
Series
AVR® ATmegar
Specifications of ATMEGA329-16MI
Core Processor
AVR
Core Size
8-Bit
Speed
16MHz
Connectivity
SPI, UART/USART, USI
Peripherals
Brown-out Detect/Reset, LCD, POR, PWM, WDT
Number Of I /o
54
Program Memory Size
32KB (16K x 16)
Program Memory Type
FLASH
Eeprom Size
1K x 8
Ram Size
2K x 8
Voltage - Supply (vcc/vdd)
2.7 V ~ 5.5 V
Data Converters
A/D 8x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
64-MLF®, 64-QFN
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
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- Download datasheet (7Mb)
7.5
7.5.1
7.5.2
7.5.3
22
Register Description
ATmega329/3290/649/6490
EEARH and EEARL – The EEPROM Address Register
EEDR – The EEPROM Data Register
EECR – The EEPROM Control Register
• Bits 15:11 – Reserved Bits
These bits are reserved bits in the ATmega329/3290/649/6490 and will always read as zero.
• Bits 10:0 – EEAR10:0: EEPROM Address
The EEPROM Address Registers – EEARH and EEARL specify the EEPROM address in the
1/2K bytes EEPROM space. The EEPROM data bytes are addressed linearly between 0 and
1023/2047. The initial value of EEAR is undefined. A proper value must be written before the
EEPROM may be accessed.
Note:
• Bits 7:0 – EEDR7:0: EEPROM Data
For the EEPROM write operation, the EEDR Register contains the data to be written to the
EEPROM in the address given by the EEAR Register. For the EEPROM read operation, the
EEDR contains the data read out from the EEPROM at the address given by EEAR.
• Bits 7:4 – Reserved Bits
These bits are reserved bits in the ATmega329/3290/649/6490 and will always read as zero.
• Bit 3 – EERIE: EEPROM Ready Interrupt Enable
Writing EERIE to one enables the EEPROM Ready Interrupt if the I bit in SREG is set. Writing
EERIE to zero disables the interrupt. The EEPROM Ready interrupt generates a constant inter-
rupt when EEWE is cleared.
• Bit 2 – EEMWE: EEPROM Master Write Enable
The EEMWE bit determines whether setting EEWE to one causes the EEPROM to be written.
When EEMWE is set, setting EEWE within four clock cycles will write data to the EEPROM at
Bit
0x22 (0x42)
0x21 (0x41)
Read/Write
Initial Value
Bit
0x20 (0x40)
Read/Write
Initial Value
Bit
0x1F (0x3F)
Read/Write
Initial Value
EEAR10 is only valid for ATmega649 and ATmega6490.
EEAR7
MSB
R/W
R/W
15
7
0
R
X
–
7
0
R
7
–
0
EEAR6
R/W
R/W
14
6
0
R
X
–
6
0
R
6
–
0
EEAR5
R/W
R/W
13
R
5
0
–
5
0
X
R
5
–
0
EEAR4
R/W
R/W
12
R
4
0
–
4
0
X
R
4
–
0
EEAR3
R/W
R/W
EERIE
11
R
3
0
R/W
–
3
0
X
3
0
EEAR10
EEAR2
EEMWE
R/W
R/W
R/W
10
2
0
2
X
X
R/W
2
0
EEAR9
EEAR1
R/W
R/W
R/W
EEWE
X
X
1
0
9
1
R/W
1
X
EEAR8
EEAR0
LSB
R/W
R/W
R/W
EERE
X
X
8
0
0
0
R/W
0
0
EEARH
EEARL
EEDR
2552K–AVR–04/11
EECR
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