AT91RM9200-QI-002 SL383 Atmel, AT91RM9200-QI-002 SL383 Datasheet - Page 27
![IC ARM MCU 16BIT 128K 208PQFP](/photos/6/73/67311/313-208-pqfp_sml.jpg)
AT91RM9200-QI-002 SL383
Manufacturer Part Number
AT91RM9200-QI-002 SL383
Description
IC ARM MCU 16BIT 128K 208PQFP
Manufacturer
Atmel
Series
AT91SAMr
Datasheets
1.AT91RM9200-EK.pdf
(41 pages)
2.AT91RM9200-DK.pdf
(2 pages)
3.AT91RM9200-QU-002.pdf
(701 pages)
Specifications of AT91RM9200-QI-002 SL383
Core Processor
ARM9
Core Size
16/32-Bit
Speed
180MHz
Connectivity
EBI/EMI, Ethernet, I²C, MMC, SPI, SSC, UART/USART, USB
Peripherals
POR
Number Of I /o
122
Program Memory Size
128KB (128K x 8)
Program Memory Type
ROM
Ram Size
48K x 8
Voltage - Supply (vcc/vdd)
1.65 V ~ 1.95 V
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
208-MQFP, 208-PQFP
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Eeprom Size
-
Data Converters
-
Other names
AT91RM9200QI002SL
10.3.5
10.3.6
10.4
10.5
1768MS–ATARM–09-Jul-09
External Bus Interface
Static Memory Controller
System Interrupt
External Interrupts
The System Interrupt is the wired-OR of the interrupt signals coming from:
The clock of these peripherals cannot be controlled and the Peripheral ID 1 can only be used
within the Advanced Interrupt Controller.
All external interrupt signals, i.e., the Fast Interrupt signal FIQ or the Interrupt signals IRQ0 to
IRQ6, use a dedicated Peripheral ID. However, there is no clock control associated with these
peripheral IDs.
• the Memory Controller
• the Debug Unit
• the System Timer
• the Real-Time Clock
• the Power Management Controller
• Integrates three External Memory Controllers:
• Additional logic for NAND Flash/SmartMedia and CompactFlash support
• Optimized External Bus:
• Configurable Chip Select Assignment:
• External memory mapping, 512-Mbyte address space
• Up to 8 Chip Select Lines
• 8- or 16-bit Data Bus
• Remap of Boot Memory
• Multiple Access Modes supported
• Multiple device adaptability
– Static Memory Controller
– SDRAM Controller
– Burst Flash Controller
– 16- or 32-bit Data Bus
– Up to 26-bit Address Bus, up to 64-Mbytes addressable
– Up to 8 Chip Selects, each reserved to one of the eight Memory Areas
– Optimized pin multiplexing to reduce latencies on External Memories
– Burst Flash Controller or Static Memory Controller on NCS0
– SDRAM Controller or Static Memory Controller on NCS1
– Static Memory Controller on NCS3, Optional NAND Flash/SmartMedia Support
– Static Memory Controller on NCS4 - NCS6, Optional CompactFlash Support
– Static Memory Controller on NCS7
– Byte Write or Byte Select Lines
– Two different Read Protocols for each Memory Bank
AT91RM9200
27