AT91RM9200-QI-002 SL383 Atmel, AT91RM9200-QI-002 SL383 Datasheet - Page 19
![IC ARM MCU 16BIT 128K 208PQFP](/photos/6/73/67311/313-208-pqfp_sml.jpg)
AT91RM9200-QI-002 SL383
Manufacturer Part Number
AT91RM9200-QI-002 SL383
Description
IC ARM MCU 16BIT 128K 208PQFP
Manufacturer
Atmel
Series
AT91SAMr
Datasheets
1.AT91RM9200-EK.pdf
(41 pages)
2.AT91RM9200-DK.pdf
(2 pages)
3.AT91RM9200-QU-002.pdf
(701 pages)
Specifications of AT91RM9200-QI-002 SL383
Core Processor
ARM9
Core Size
16/32-Bit
Speed
180MHz
Connectivity
EBI/EMI, Ethernet, I²C, MMC, SPI, SSC, UART/USART, USB
Peripherals
POR
Number Of I /o
122
Program Memory Size
128KB (128K x 8)
Program Memory Type
ROM
Ram Size
48K x 8
Voltage - Supply (vcc/vdd)
1.65 V ~ 1.95 V
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
208-MQFP, 208-PQFP
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Eeprom Size
-
Data Converters
-
Other names
AT91RM9200QI002SL
9. System Peripherals
9.1
9.2
9.3
1768MS–ATARM–09-Jul-09
Reset Controller
Advanced Interrupt Controller
Power Management Controller
A complete memory map is shown in
• Two reset input lines (NRST and NTRST) providing, respectively:
• Initialization of the User Interface registers (defined in the user interface of each peripheral)
• Initialization of the embedded ICE TAP controller
• Controls the interrupt lines (nIRQ and nFIQ) of an ARM Processor
• Thirty-two individually maskable and vectored interrupt sources
• 8-level Priority Controller
• Vectoring
• Protect Mode
• General Interrupt Mask
• Optimizes the power consumption of the whole system
• Embeds and controls:
• Provides:
and:
– Sample the signals needed at bootup
– Compel the processor to fetch the next instruction at address zero
– Source 0 is reserved for the Fast Interrupt Input (FIQ)
– Source 1 is reserved for system peripherals (ST, RTC, PMC, DBGU…)
– Source 2 to Source 31 control thirty embedded peripheral interrupts or external
– Programmable Edge-triggered or Level-sensitive Internal Sources
– Programmable Positive/Negative Edge-triggered or High/Low Level-sensitive
– Drives the Normal Interrupt of the processor
– Handles priority of the interrupt sources 1 to 31
– Higher priority interrupts can be served during service of lower priority interrupt
– Optimizes Interrupt Service Routine Branch and Execution
– One 32-bit Vector Register per interrupt source
– Interrupt Vector Register reads the corresponding current Interrupt Vector
– Easy debugging by preventing automatic operations
– Provides processor synchronization on events without triggering an interrupt
– One Main Oscillator and One Slow Clock Oscillator (32.768Hz)
– Two Phase Locked Loops (PLLs) and Dividers
– Clock Prescalers
– the Processor Clock PCK
interrupts
External Sources
Figure 8-1 on page
17.
AT91RM9200
19