AT91RM9200-QI-002 SL383 Atmel, AT91RM9200-QI-002 SL383 Datasheet - Page 15
![IC ARM MCU 16BIT 128K 208PQFP](/photos/6/73/67311/313-208-pqfp_sml.jpg)
AT91RM9200-QI-002 SL383
Manufacturer Part Number
AT91RM9200-QI-002 SL383
Description
IC ARM MCU 16BIT 128K 208PQFP
Manufacturer
Atmel
Series
AT91SAMr
Datasheets
1.AT91RM9200-EK.pdf
(41 pages)
2.AT91RM9200-DK.pdf
(2 pages)
3.AT91RM9200-QU-002.pdf
(701 pages)
Specifications of AT91RM9200-QI-002 SL383
Core Processor
ARM9
Core Size
16/32-Bit
Speed
180MHz
Connectivity
EBI/EMI, Ethernet, I²C, MMC, SPI, SSC, UART/USART, USB
Peripherals
POR
Number Of I /o
122
Program Memory Size
128KB (128K x 8)
Program Memory Type
ROM
Ram Size
48K x 8
Voltage - Supply (vcc/vdd)
1.65 V ~ 1.95 V
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
208-MQFP, 208-PQFP
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Eeprom Size
-
Data Converters
-
Other names
AT91RM9200QI002SL
7.3
7.4
7.5
1768MS–ATARM–09-Jul-09
Boot Program
Embedded Software Services
Memory Controller
• Debug Unit
• Embedded Trace Macrocell: ETM9
• IEEE1149.1 JTAG Boundary Scan on all Digital Pins
• Default Boot Program stored in ROM-based products
• Downloads and runs an application from external storage media into internal SRAM
• Downloaded code size depends on embedded SRAM size
• Automatic detection of valid application
• Bootloader supporting a wide range of non-volatile memories
• Boot Uploader in case no valid program is detected in external NVM and supporting several
• Serial communication on a DBGU (XModem protocol)
• USB Device Port (DFU Protocol)
• Compliant with ATPCS
• Compliant with AINSI/ISO Standard C
• Compiled in ARM/Thumb Interworking
• ROM Entry Service
• Tempo, Xmodem and DataFlash services
• CRC and Sine tables
• Programmable Bus Arbiter handling four Masters
communication media
– Two-pin UART
– Debug Communication Channel
– Chip ID Register
– Medium Level Implementation
– Half-rate Clock Mode
– Four Pairs of Address Comparators
– Two Data Comparators
– Eight Memory Map Decoder Inputs
– Two Counters
– One Sequencer
– One 18-byte FIFO
– SPI DataFlash
– Two-wire EEPROM
– 8-bit parallel memories on NCS0
– Internal Bus is shared by ARM920T, PDC, USB Host Port and Ethernet MAC
– Each Master can be assigned a priority between 0 and 7
Masters
®
connected on SPI NPCS0
™
Rev2a
AT91RM9200
15