AT91SAM7A2-AU Atmel, AT91SAM7A2-AU Datasheet - Page 5

• Manufacturer Part Number: AT91SAM7A2-AU
• Description: IC ARM7 MCU 32BIT ROMLESS176LQFP
• Manufacturer: Atmel
• Series: AT91SAMr

Specifications of AT91SAM7A2-AU

• Core Processor: ARM7
• Core Size: 16/32-Bit
• Speed: 30MHz
• Connectivity: CAN, EBI/EMI, SPI, UART/USART
• Peripherals: POR, PWM, WDT
• Number Of I /o: 57
• Program Memory Type: ROMless
• Ram Size: 16K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 176-LQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -

Signal Description
Table 2. Signal Description
6021BS–ATARM–06-Jul-04
Module
EBI
GIC
Power-on
Reset
Master Clock
32.768 kHz
clock
PIO
USART0
USART1
Capture0
Capture1
PWM
Timer T0
Name
ADD[19:1]
ADD0/NLB
ADD20/CS3
D[15:0]
NOE
NWR0/NWE
NCS[2:0]
NWR1/NUB
NWAIT
CORECLK
IRQ[1:0]
FIQ
NRESET
MCKI
MCKO
PLLRC
RTCKI
RTCKO
UPIO[31:0]
SCK0/MPIO
RXD0/MPIO
TXD0/MPIO
SCK1/MPIO
RXD1/MPIO
TXD1/MPIO
CAPT0
CAPT1
PWM[3:0]
T0TIOA[2:0]/MPIO Capture/waveform I/O
T0TIOB[2:0]/MPIO Trigger/waveform I/O
T0TIOCLK[2:0]/MP
IO
Function
External address bus
Lower byte enable
External data bus
Output enable
Chip select lines
Upper byte enable
Core CLock
Fast interrupt line
Master clock input
Master clock output
PLL RC network input
32.768 KHz clock input
32.768 KHz clock output
USART0 clock line
USART1 clock line
External clock/trigger/input
External address line line/
External address line/ Chip select
Write enable
External Wait
External interrupt lines
Hardware reset input
General purpose I/O
USART0 receive line
USART0 transmit line
USART1 receive line
USART1 transmit line
Capture input
Capture input
Pulse Width Modulation output
Type
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
O
O
O
O
O
O
O
O
O
O
O
I
I
I
I
I
I
I
I
I
Active
AT91SAM7A2 - Summary
Level Comments
H (Z)
(Z)
L (Z)
L (Z)
L (Z)
L (Z)
L (Z)
(Z)
(Z)
(Z)
(Z)
(Z)
(Z)
(Z)
(Z)
(L)
(Z)
(Z)
(Z)
L
L
(1)
PRELIMINARY
The EBI is tri-stated when NRESET is at a
logical low level.
Internal pull-downs on data bus bits
Disable at reset, multiplexed with UPIO30
Disable at reset, multiplexed with UPIO31
Connected to external crystal (4 to 6 Mhz)
Connected to external 32.768 Khz crystal
Multiplexed with general purpose I/O
Multiplexed with general purpose I/O
Multiplexed with general purpose I/O
Multiplexed with general purpose I/O
Multiplexed with general purpose I/O
Multiplexed with general purpose I/O
Multiplexed with a general purpose I/O
Multiplexed with a general purpose I/O
Multiplexed with a general purpose I/O
Schmitt input with internal filter
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