ATAM893T-TKS Atmel, ATAM893T-TKS Datasheet - Page 79
![IC MON TIRE-PRESS ATARX9X SER](/photos/6/91/69198/453-20-ssop_sml.jpg)
ATAM893T-TKS
Manufacturer Part Number
ATAM893T-TKS
Description
IC MON TIRE-PRESS ATARX9X SER
Manufacturer
Atmel
Series
MARC4r
Datasheet
1.ATAM893T-TKS.pdf
(98 pages)
Specifications of ATAM893T-TKS
Core Processor
MARC4
Core Size
4-Bit
Speed
4MHz
Connectivity
SSI (2-Wire, 3 Wire)
Peripherals
Brown-out Detect/Reset, POR, PWM, WDT
Number Of I /o
16
Program Memory Size
4KB (4K x 8)
Program Memory Type
EEPROM
Eeprom Size
64 x 16
Ram Size
256 x 4
Voltage - Supply (vcc/vdd)
1.8 V ~ 6.5 V
Oscillator Type
Internal
Operating Temperature
-40°C ~ 125°C
Package / Case
20-SOIC (5.3mm Width), 20-SO, 20-SOEIAJ
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Data Converters
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4680C–4BMCU–01/05
Combination Mode 9: Bi-phase Demodulation
SSI mode 1:
Timer 3 mode 11:
In the Bi-phase demodulation mode the timer works like in the Manchester demodulation mode.
The difference is that the bits are decoded with the toggle flip-flop. This flip-flop samples the
edge in the middle of the bit-frame and the compare register 1 match event shifts the toggle flip-
flop output into shift register. Before activating the demodulation the timer and the demodulation
stage must be synchronized with the bit-stream. The Bi-phase code timing consists of parts with
the half bit-length and the complete bit-length. The synchronization routine must start the
demodulator after an interval with the complete bit-length.
The counter can be driven by any internal clock source and the output T3O can be used by
Timer 2 in this mode.
Figure 5-58. Bi-phase Demodulation
CM31 = SCI
Counter 3
SR-DATA
Q1 = SI
Timer 3
Reset
mode
T3EX
T3I
Synchronize
8-bit shift register internal data input (SI) and the internal shift clock
(SCI) from the Timer 3
Bi-phase demodulation with Timer 3
0
0
Bit 7
0
1
Bit 6
1
1
Bi-phase demodulation mode
Bit 5
1
0
Bit 4
0
1
Bit 3
1
0
Bit 2
ATAM893-D
0
1
Bit 1
1
0
Bit 0
0
79
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