AT89C51RC2-RLTIM Atmel, AT89C51RC2-RLTIM Datasheet - Page 69
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AT89C51RC2-RLTIM
Manufacturer Part Number
AT89C51RC2-RLTIM
Description
IC 8051 MCU FLASH 32K 44VQFP
Manufacturer
Atmel
Series
89Cr
Datasheet
1.AT89C51RB2-RLTIL.pdf
(127 pages)
Specifications of AT89C51RC2-RLTIM
Core Processor
8051
Core Size
8-Bit
Speed
60MHz
Connectivity
SPI, UART/USART
Peripherals
POR, PWM, WDT
Number Of I /o
32
Program Memory Size
32KB (32K x 8)
Program Memory Type
FLASH
Ram Size
1.25K x 8
Voltage - Supply (vcc/vdd)
2.7 V ~ 5.5 V
Oscillator Type
External
Operating Temperature
-40°C ~ 85°C
Package / Case
44-TQFP, 44-VQFP
For Use With
AT89STK-11 - KIT STARTER FOR AT89C51RX2
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Eeprom Size
-
Data Converters
-
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Baud Rate
4180E–8051–10/06
drive the network. The Master may select each Slave device by software through port
pins (Figure 26). To prevent bus conflicts on the MISO line, only one slave should be
selected at a time by the Master for a transmission.
In a Master configuration, the SS line can be used in conjunction with the MODF flag in
the SPI Status register (SPSTA) to prevent multiple masters from driving MOSI and
SCK (see Error conditions).
A high level on the SS pin puts the MISO line of a Slave SPI in a high-impedance state.
The SS pin could be used as a general-purpose if the following conditions are met:
•
•
Note:
In Master mode, the baud rate can be selected from a baud rate generator which is con-
trolled by three bits in the SPCON register: SPR2, SPR1 and SPR0.The Master clock is
selected from one of seven clock rates resulting from the division of the internal clock by
2, 4, 8, 16, 32, 64 or 128.
Table 54 gives the different clock rates selected by SPR2:SPR1:SPR0.
Table 54. SPI Master Baud Rate Selection
SPR2
The device is configured as a Master and the SSDIS control bit in SPCON is set.
This kind of configuration can be found when only one Master is driving the network
and there is no way that the SS pin could be pulled low. Therefore, the MODF flag in
the SPSTA will never be set
The Device is configured as a Slave with CPHA and SSDIS control bits set
kind of configuration can happen when the system comprises one Master and one
Slave only. Therefore, the device should always be selected and there is no reason
that the Master uses the SS pin to select the communicating Slave device.
0
0
0
0
1
1
1
1
1. Clearing SSDIS control bit does not clear MODF.
2. Special care should be taken not to set SSDIS control bit when CPHA = ’0’ because
in this mode, the SS is used to start the transmission.
SPR1
0
0
1
1
0
0
1
1
SPR0
0
1
0
1
0
1
0
1
(1)
.
F
F
F
F
F
F
CLK PERIPH
F
Clock Rate
CLK PERIPH
CLK PERIPH
CLK PERIPH
CLK PERIPH
CLK PERIPH
CLK PERIPH
Don’t Use
/128
/16
/32
/64
/8
/2
/4
AT89C51RB2/RC2
Baud Rate Divisor (BD)
No BRG
128
16
32
64
2
4
8
(2)
. This
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