DSPIC30F6011T-20I/PF Microchip Technology, DSPIC30F6011T-20I/PF Datasheet - Page 6

• Manufacturer Part Number: DSPIC30F6011T-20I/PF
• Description: IC DSPIC MCU/DSP 132K 64TQFP
• Manufacturer: Microchip Technology
• Series: dsPIC™ 30Fr

Specifications of DSPIC30F6011T-20I/PF

• Core Processor: dsPIC
• Core Size: 16-Bit
• Speed: 20 MIPS
• Connectivity: CAN, I²C, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, LVD, POR, PWM, WDT
• Number Of I /o: 52
• Program Memory Size: 132KB (44K x 24)
• Program Memory Type: FLASH
• Eeprom Size: 2K x 8
• Ram Size: 6K x 8
• Voltage - Supply (vcc/vdd): 2.5 V ~ 5.5 V
• Data Converters: A/D 16x12b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 64-TQFP, 64-VQFP
• For Use With: XLT64PT4 - SOCKET TRAN ICE 64MQFP/TQFPAC164313 - MODULE SKT FOR PM3 64PFAC30F002 - MODULE SOCKET DSPIC30F 64TQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: DSPIC30F6011T20IP

dsPIC30F6011/6012/6013/6014
10. Module: Interrupting a
EXAMPLE 11:
EXAMPLE 12:
DS80183D-page 6
__T1Interrupt:
__T1Interrupt:
When
NSTDIS(INTCON1<15>) bit is ‘0’), the following
sequence of events will lead to an Address Error
trap:
1. REPEAT-loop is active
2. An interrupt is generated during the execution
3. The CPU executes the Interrupt Service
4. Within the ISR, when the CPU is executing the
Work around
Processing of Interrupt Service Routines should
be disabled while the RETFIE instruction is being
executed. This may be accomplished in two
different ways:
1. Place a DISI instruction immediately before
2. Immediately prior to executing the RETFIE
PUSH
.......
BCLR
POP
DISI
RETFIE
PUSH
.......
BCLR
MOV.B
MOV.B
POP
RETFIE
of the REPEAT-loop.
Routine (ISR) of the source causing the
interrupt.
first instruction cycle of the 3-cycle RETFIE
(Return-from-interrupt) instruction, a second
interrupt is generated by a source with a higher
interrupt priority.
the RETFIE instruction in all interrupt service
routines of interrupt sources that may be inter-
rupted by other higher priority interrupt sources
(with priority levels 1 through 6). This is shown
in Example 11 in the Timer1 ISR. In this exam-
ple, a DISI instruction inhibits level 1 through
level 6 interrupts for 2 instruction cycles, while
the RETFIE instruction is executed.
instruction, increase the CPU priority level by
modifying the IPL<2:0> (SR<7:5>) bits to ‘111’
as shown in Example 12. This will disable all
interrupts between priority levels 1 through 7.
interrupt
W0
IFS0, #T1IF
W0
#1
W0
IFS0, #T1IF
#0xE0, W0
WREG, SR
W0
;Another interrupt occurs
;here and it is processed
;correctly
;Another interrupt occurs
;here and it is processed
;correctly
;Timer1 ISR
;This line optional
;This line optional
;Timer1 ISR
nesting
REPEAT
is
enabled
Loop
Advance Information
(or
11. Module: 32-bit General Purpose Timers
12. Module: 12-bit 100 Ksps A/D Converter
Pairs of 16-bit timers may be combined to form
32-bit timers. For example, Timer2 and Timer3 are
combined into a single 32-bit timer. For this
release of silicon, when a 32-bit timer is prescaled
by ratios other than 1:1, unexpected results may
occur.
Work around
None. The application may only use the 1:1
prescaler for 32-bit timers.
Input Channel Scanning allows the A/D converter
to acquire and convert signals on a selected set of
“MUX A” input pins in sequence. This function is
controlled by the CSCNA (ADCON2<11>) bit and
the ADCSSL SFR.
The ALTS (ADCON2<0>) bit, when set, allows the
A/D converter to alternately acquire and convert a
“MUX A” input signal and a “MUX B” input signal in
an interleaved fashion.
When both CSCNA and ALTS are set, the A/D
module should scan MUX A input pins while
alternating with a fixed MUX B input pin. However,
for this release of silicon, when both features are
enabled simultaneously, the last input pin enabled
for channel scanning in the ADCSSL SFR, is not
scanned. Thus, the A/D converter converts one
channel less than the number specified in the scan
sequence. Note that this erratum does not affect
devices that have a 10-bit 500 Ksps A/D converter.
Work around
The user may enable an extra (“dummy”) input pin
in the channel-scanning sequence. For example, if
it is desirable to scan pins AN3, AN4 and AN5 on
the set of MUX A inputs while interleaving conver-
sion from AN6 on the MUX B input, the user may
configure the A/D converter as follows:
For the configuration above, AN15 is the dummy
input that will not be scanned. On the A/D interrupt,
the A/D buffer will contain conversions from the
following pins in sequence:
- ADCON2 = 0x041D
- ADCHS = 0x0600
- ADCSSL = 0x8038
- ADCBUF0 = AN3
- ADCBUF1 = AN6
- ADCBUF2 = AN4
- ADCBUF3 = AN6
- ADCBUF4 = AN5
- ADCBUF5 = AN6
- ADCBUF6 = AN3
- ADCBUF7 = AN6
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