DSPIC30F6011T-20I/PF Microchip Technology, DSPIC30F6011T-20I/PF Datasheet - Page 11
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DSPIC30F6011T-20I/PF
Manufacturer Part Number
DSPIC30F6011T-20I/PF
Description
IC DSPIC MCU/DSP 132K 64TQFP
Manufacturer
Microchip Technology
Series
dsPIC™ 30Fr
Datasheets
1.DSPIC30F2011-20ISO.pdf
(66 pages)
2.DSPIC30F5011T-20IPT.pdf
(34 pages)
3.DSPIC30F6010T-20IPF.pdf
(6 pages)
4.DSPIC30F6011T-20IPF.pdf
(12 pages)
5.DSPIC30F6011T-20IPF.pdf
(226 pages)
Specifications of DSPIC30F6011T-20I/PF
Core Processor
dsPIC
Core Size
16-Bit
Speed
20 MIPS
Connectivity
CAN, I²C, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, LVD, POR, PWM, WDT
Number Of I /o
52
Program Memory Size
132KB (44K x 24)
Program Memory Type
FLASH
Eeprom Size
2K x 8
Ram Size
6K x 8
Voltage - Supply (vcc/vdd)
2.5 V ~ 5.5 V
Data Converters
A/D 16x12b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
64-TQFP, 64-VQFP
For Use With
XLT64PT4 - SOCKET TRAN ICE 64MQFP/TQFPAC164313 - MODULE SKT FOR PM3 64PFAC30F002 - MODULE SOCKET DSPIC30F 64TQFP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Other names
DSPIC30F6011T20IP
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
DSPIC30F6011T-20I/PF
Manufacturer:
Microchip Technology
Quantity:
10 000
15. Page 5-12, Section 5.4.2.3 Loading Write
2004 Microchip Technology Inc.
On page 5-12, Section 5.4.2.3 Loading Write
Latches should be replaced with the following:
Latches
5.4.2.3 Loading Write Latches
The following is a sequence of instructions that can be used to load the 768-bits of write latches
(32 instruction words). Four TBLWTL and four TBLWTH instructions are needed to load the write
latches selected by the table pointer.
The TBLPAG register is loaded with the 8 MSbits of the program memory address. The user
does not need to write the NVMADRU:NVMADR register-pair for a Flash programming opera-
tion. The 24-bits of the program memory address are automatically captured into the
NVMADRU:NVMADR register-pair when each table write instruction is executed. The program
memory must be programmed at an ‘even’ 32 instruction word address boundary. In effect, the
6 LSbits of the value captured in the NVMADR register are not used during the programming
operation.
The row of 32 instruction words do not necessarily have to be written in sequential order. The
6 LSbits of the table write address determine which of the latches will be written. However, all 32
instruction words should be written for each programming cycle to overwrite old data.
; Set up a pointer to the first program memory location to be written.
MOV
MOV
MOV
; Perform the TBLWT instructions to write the latches
; W0 is incremented in the TBLWTH instruction to point to the
; next instruction location.
MOV
MOV
TBLWTL W2
TBLWTH W3
MOV
MOV
TBLWTL W2
TBLWTH W3,[W0++]
MOV
MOV
TBLWTL W2
TBLWTH W3
MOV
MOV
TBLWTL W2
TBLWTH W3,[W0++]
........
........
MOV
MOV
TBLWTL W2
TBLWTH W3,[W0++]
Note:
#tblpage(PROG_ADDR),W0
W0
#tbloffset(PROG_ADDR),W0
#LOW_WORD_0,W2
#HIGH_BYTE_0,W3
#LOW_WORD_1,W2
#HIGH_BYTE_1,W3
#LOW_WORD_2,W2
#HIGH_BYTE_2,W3
#LOW_WORD_3,W2
#HIGH_BYTE_3,W3
#LOW_WORD_31,W2
#HIGH_BYTE_31,W3
The following code example is the ‘Load_Write_Latch’ code referred to in subquent
examples.
,
,
,
,
,
,
,
,
TBLPAG
[W0]
[W0++]
[W0]
[W0]
[W0]
[W0]
[W0++]
dsPIC30F Family Reference Manual
; 1st_program_word
; 2nd_program_word
; 3rd_program_word
; 4th_program_word
; 32nd_program_word
DS80169E-page 11