PIC18LF4539T-I/ML Microchip Technology, PIC18LF4539T-I/ML Datasheet - Page 82
![IC MCU FLASH 12KX16 EE A/D 44QFN](/photos/6/81/68122/150-44-qfn_sml.jpg)
PIC18LF4539T-I/ML
Manufacturer Part Number
PIC18LF4539T-I/ML
Description
IC MCU FLASH 12KX16 EE A/D 44QFN
Manufacturer
Microchip Technology
Series
PIC® 18Fr
Datasheets
1.PIC16LF627A-IP.pdf
(8 pages)
2.PIC18F2439-ISO.pdf
(322 pages)
3.PIC18F2439-ISO.pdf
(6 pages)
Specifications of PIC18LF4539T-I/ML
Core Processor
PIC
Core Size
8-Bit
Speed
40MHz
Connectivity
I²C, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, LVD, POR, PWM, WDT
Number Of I /o
32
Program Memory Size
24KB (12K x 16)
Program Memory Type
FLASH
Eeprom Size
256 x 8
Ram Size
1408 x 8
Voltage - Supply (vcc/vdd)
2 V ~ 5.5 V
Data Converters
A/D 8x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
44-QFN
Processor Series
PIC18LF
Core
PIC
Data Bus Width
8 bit
Data Ram Size
1408 B
Interface Type
I2C, SPI, AUSART
Maximum Clock Frequency
40 MHz
Number Of Programmable I/os
32
Number Of Timers
16 bit
Operating Supply Voltage
2 V to 5.5 V
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
3rd Party Development Tools
52715-96, 52716-328, 52717-734, 52712-325, EWPIC18
Development Tools By Supplier
DV164005, DV164136
Minimum Operating Temperature
- 40 C
On-chip Adc
8
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
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PIC18FXX39
8.5
The RCON register contains the bit which is used to
enable prioritized interrupts (IPEN). For PIC18FXX39
devices, the IPEN bit must always be set (= 1) for the
ProMPT kernel to function correctly. Refer to page 69
for a more detailed discussion on interrupt priorities.
REGISTER 8-10:
DS30485A-page 80
RCON Register
bit 7
bit 6-5
bit 4
bit 3
bit 2
bit 1
bit 0
RCON REGISTER
IPEN
1 = Enable priority levels on interrupts
0 = Disable priority levels on interrupts (not used)
Unimplemented: Read as '0'
RI: RESET Instruction Flag bit
For details of bit operation, see Register 4-3
TO: Watchdog Time-out Flag bit
For details of bit operation, see Register 4-3
PD: Power-down Detection Flag bit
For details of bit operation, see Register 4-3
POR: Power-on Reset Status bit
For details of bit operation, see Register 4-3
BOR: Brown-out Reset Status bit
For details of bit operation, see Register 4-3
Legend:
R = Readable bit
- n = Value at POR
bit 7
IPEN
R/W-0
Note 1: Maintain this bit set (= 1).
(1)
(1)
: Interrupt Priority Enable bit
U-0
—
U-0
Preliminary
—
W = Writable bit
‘1’ = Bit is set
R/W-1
RI
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared
R-1
TO
R-1
PD
2002 Microchip Technology Inc.
x = Bit is unknown
R/W-0
POR
R/W-0
BOR
bit 0
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