PIC18LF4539T-I/ML Microchip Technology, PIC18LF4539T-I/ML Datasheet - Page 253
![IC MCU FLASH 12KX16 EE A/D 44QFN](/photos/6/81/68122/150-44-qfn_sml.jpg)
PIC18LF4539T-I/ML
Manufacturer Part Number
PIC18LF4539T-I/ML
Description
IC MCU FLASH 12KX16 EE A/D 44QFN
Manufacturer
Microchip Technology
Series
PIC® 18Fr
Datasheets
1.PIC16LF627A-IP.pdf
(8 pages)
2.PIC18F2439-ISO.pdf
(322 pages)
3.PIC18F2439-ISO.pdf
(6 pages)
Specifications of PIC18LF4539T-I/ML
Core Processor
PIC
Core Size
8-Bit
Speed
40MHz
Connectivity
I²C, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, LVD, POR, PWM, WDT
Number Of I /o
32
Program Memory Size
24KB (12K x 16)
Program Memory Type
FLASH
Eeprom Size
256 x 8
Ram Size
1408 x 8
Voltage - Supply (vcc/vdd)
2 V ~ 5.5 V
Data Converters
A/D 8x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
44-QFN
Processor Series
PIC18LF
Core
PIC
Data Bus Width
8 bit
Data Ram Size
1408 B
Interface Type
I2C, SPI, AUSART
Maximum Clock Frequency
40 MHz
Number Of Programmable I/os
32
Number Of Timers
16 bit
Operating Supply Voltage
2 V to 5.5 V
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
3rd Party Development Tools
52715-96, 52716-328, 52717-734, 52712-325, EWPIC18
Development Tools By Supplier
DV164005, DV164136
Minimum Operating Temperature
- 40 C
On-chip Adc
8
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
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TSTFSZ
Syntax:
Operands:
Operation:
Status Affected:
Encoding:
Description:
Words:
Cycles:
Example:
2002 Microchip Technology Inc.
Q Cycle Activity:
If skip:
If skip and followed by 2-word instruction:
Before Instruction
After Instruction
operation
operation
operation
Decode
PC = Address (HERE)
If CNT
PC
If CNT
PC
No
No
No
Q1
Q1
Q1
register 'f'
operation
operation
operation
Test f, skip if 0
[ label ] TSTFSZ f [,a]
0 ≤ f ≤ 255
a ∈ [0,1]
skip if f = 0
None
If 'f' = 0, the next instruction,
fetched during the current instruc-
tion execution, is discarded and a
NOP is executed, making this a two-
cycle instruction. If ‘a’ is 0, the
Access Bank will be selected, over-
riding the BSR value. If ‘a’ is 1,
then the bank will be selected as
per the BSR value (default).
1
1(2)
Note: 3 cycles if skip and followed
HERE
NZERO
ZERO
Read
0110
No
No
No
Q2
Q2
Q2
=
=
≠
=
by a 2-word instruction.
0x00,
Address (ZERO)
0x00,
Address (NZERO)
:
TSTFSZ
:
011a
operation
operation
operation
Process
Data
No
No
No
Q3
Q3
Q3
CNT, 1
ffff
operation
operation
operation
operation
No
No
No
No
Q4
Q4
Q4
ffff
Preliminary
XORLW
Syntax:
Operands:
Operation:
Status Affected:
Encoding:
Description:
Words:
Cycles:
Example:
Q Cycle Activity:
Before Instruction
After Instruction
Decode
W
W
Q1
=
=
literal 'k'
Exclusive OR literal with W
[ label ] XORLW k
0 ≤ k ≤ 255
(W) .XOR. k → W
N, Z
The contents of W are XORed
with the 8-bit literal 'k'. The result
is placed in W.
1
1
XORLW 0xAF
Read
Q2
PIC18FXX39
0000
0xB5
0x1A
1010
Process
Data
Q3
DS30485A-page 251
kkkk
Write to W
Q4
kkkk
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