T89C51CC01CA-RLTIM Atmel, T89C51CC01CA-RLTIM Datasheet - Page 39
![IC 8051 MCU FLASH 32K 44VQFP](/photos/6/92/69202/313-44-vqfp_sml.jpg)
T89C51CC01CA-RLTIM
Manufacturer Part Number
T89C51CC01CA-RLTIM
Description
IC 8051 MCU FLASH 32K 44VQFP
Manufacturer
Atmel
Series
AT89C CANr
Datasheets
1.T89C51CC01CA-7CTIM.pdf
(167 pages)
2.T89C51CC01CA-7CTIM.pdf
(12 pages)
3.T89C51CC01CA-7CTIM.pdf
(32 pages)
4.T89C51CC01CA-7CTIM.pdf
(29 pages)
Specifications of T89C51CC01CA-RLTIM
Core Processor
8051
Core Size
8-Bit
Speed
40MHz
Connectivity
CAN, UART/USART
Peripherals
POR, PWM, WDT
Number Of I /o
32
Program Memory Size
32KB (32K x 8)
Program Memory Type
FLASH
Eeprom Size
2K x 8
Ram Size
1.25K x 8
Voltage - Supply (vcc/vdd)
3 V ~ 5.5 V
Data Converters
A/D 8x10b
Oscillator Type
External
Operating Temperature
-40°C ~ 85°C
Package / Case
44-TQFP, 44-VQFP
For Use With
AT89STK-06 - KIT DEMOBOARD 8051 MCU W/CAN
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Other names
T89C51CC01CARLTIM
Available stocks
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Manufacturer
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- T89C51CC01CA-7CTIM PDF datasheet
- T89C51CC01CA-7CTIM PDF datasheet #2
- T89C51CC01CA-7CTIM PDF datasheet #3
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Programming the Flash Spaces
User
Extra Row
4129N–CAN–03/08
Figure 21. Column Latches Loading Procedure
Note:
The following procedure is used to program the User space and is summarized in
Figure 22:
•
•
•
•
The following procedure is used to program the Extra Row space and is summarized in
Figure 22:
•
•
•
•
Load up to one page of data in the column latches from address 0000h to 7FFFh.
Save then disable the interrupts.
Launch the programming by writing the data sequence 50h followed by A0h in
FCON register (only from FM1).
The end of the programming indicated by the FBUSY flag cleared.
Restore the interrupts.
Load data in the column latches from address FF80h to FFFFh.
Save then disable the interrupts.
Launch the programming by writing the data sequence 52h followed by A2h in
FCON register. This step of the procedure must be executed from FM1. The end of
the programming indicated by the FBUSY flag cleared.
The end of the programming indicated by the FBUSY flag cleared.
Restore the interrupts.
The last page address used when loading the column latch is the one used to select the
page programming address.
Data memory Mapping
Column Latches Mapping
FCON = 00h (FPS = 0)
Exec: MOVX @DPTR, A
FCON = 08h (FPS=1)
Column Latches
Save and Disable IT
DPTR = Address
ACC = Data
Last Byte
Data Load
to load?
Restore IT
Loading
EA = 0
39
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