T89C51CC01CA-RLTIM Atmel, T89C51CC01CA-RLTIM Datasheet - Page 14
![IC 8051 MCU FLASH 32K 44VQFP](/photos/6/92/69202/313-44-vqfp_sml.jpg)
T89C51CC01CA-RLTIM
Manufacturer Part Number
T89C51CC01CA-RLTIM
Description
IC 8051 MCU FLASH 32K 44VQFP
Manufacturer
Atmel
Series
AT89C CANr
Datasheets
1.T89C51CC01CA-7CTIM.pdf
(167 pages)
2.T89C51CC01CA-7CTIM.pdf
(12 pages)
3.T89C51CC01CA-7CTIM.pdf
(32 pages)
4.T89C51CC01CA-7CTIM.pdf
(29 pages)
Specifications of T89C51CC01CA-RLTIM
Core Processor
8051
Core Size
8-Bit
Speed
40MHz
Connectivity
CAN, UART/USART
Peripherals
POR, PWM, WDT
Number Of I /o
32
Program Memory Size
32KB (32K x 8)
Program Memory Type
FLASH
Eeprom Size
2K x 8
Ram Size
1.25K x 8
Voltage - Supply (vcc/vdd)
3 V ~ 5.5 V
Data Converters
A/D 8x10b
Oscillator Type
External
Operating Temperature
-40°C ~ 85°C
Package / Case
44-TQFP, 44-VQFP
For Use With
AT89STK-06 - KIT DEMOBOARD 8051 MCU W/CAN
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Other names
T89C51CC01CARLTIM
Available stocks
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- T89C51CC01CA-7CTIM PDF datasheet
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Clock
Description
14
A/T89C51CC01
The T89C51CC01 core needs only 6 clock periods per machine cycle. This feature,
called ”X2”, provides the following advantages:
•
•
•
•
In order to keep the original C51 compatibility, a divider-by-2 is inserted between the
XTAL1 signal and the main clock input of the core (phase generator). This divider may
be disabled by the software.
An extra feature is available to start after Reset in the X2 mode. This feature can be
enabled by a bit X2B in the Hardware Security Byte. This bit is described in the section
"In-System-Programming".
The X2 bit in the CKCON register (see Table 12) allows switching from 12 clock cycles
per instruction to 6 clock cycles and vice versa. At reset, the standard speed is activated
(STD mode).
Setting this bit activates the X2 feature (X2 mode) for the CPU Clock only (see Figure
5.).
The Timers 0, 1 and 2, Uart, PCA, Watchdog or CAN switch in X2 mode only if the cor-
responding bit is cleared in the CKCON register.
The clock for the whole circuit and peripheral is first divided by two before being used by
the CPU core and peripherals. This allows any cyclic ratio to be accepted on the XTAL1
input. In X2 mode, as this divider is bypassed, the signals on XTAL1 must have a cyclic
ratio between 40 to 60%. Figure 5. shows the clock generation block diagram. The X2
bit is validated on the XTAL1÷2 rising edge to avoid glitches when switching from the X2
to the STD mode. Figure 6 shows the mode switching waveforms.
Divides frequency crystals by 2 (cheaper crystals) while keeping the same CPU
power.
Saves power consumption while keeping the same CPU power (oscillator power
saving).
Saves power consumption by dividing dynamic operating frequency by 2 in
operating and idle modes.
Increases CPU power by 2 while keeping the same crystal frequency.
4129N–CAN–03/08
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