PIC18C658-E/PT Microchip Technology, PIC18C658-E/PT Datasheet - Page 91
![IC MCU OTP 16KX16 CAN 64TQFP](/photos/6/81/68123/c04-066_pf_sml.jpg)
PIC18C658-E/PT
Manufacturer Part Number
PIC18C658-E/PT
Description
IC MCU OTP 16KX16 CAN 64TQFP
Manufacturer
Microchip Technology
Series
PIC® 18Cr
Datasheets
1.PIC16F616T-ISL.pdf
(8 pages)
2.PIC16C770-ISO.pdf
(8 pages)
3.PIC18C658-IPT.pdf
(366 pages)
4.PIC18C658-IPT.pdf
(16 pages)
5.PIC18C658-IPT.pdf
(16 pages)
6.PIC18C658-IPT.pdf
(16 pages)
Specifications of PIC18C658-E/PT
Core Processor
PIC
Core Size
8-Bit
Speed
40MHz
Connectivity
CAN, I²C, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, LVD, POR, PWM, WDT
Number Of I /o
52
Program Memory Size
32KB (16K x 16)
Program Memory Type
OTP
Ram Size
1.5K x 8
Voltage - Supply (vcc/vdd)
4.2 V ~ 5.5 V
Data Converters
A/D 12x10b
Oscillator Type
External
Operating Temperature
-40°C ~ 125°C
Package / Case
64-TFQFP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Other names
PIC18C658E/PT
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
PIC18C658-E/PT
Manufacturer:
Microchip Technology
Quantity:
10 000
- PIC16F616T-ISL PDF datasheet
- PIC16C770-ISO PDF datasheet #2
- PIC18C658-IPT PDF datasheet #3
- PIC18C658-IPT PDF datasheet #4
- PIC18C658-IPT PDF datasheet #5
- PIC18C658-IPT PDF datasheet #6
- Current page: 91 of 366
- Download datasheet (7Mb)
8.2
PORTB is an 8-bit wide bi-directional port. The corre-
sponding Data Direction register is TRISB. Setting a
TRISB bit (=1) will make the corresponding PORTB pin
an input (i.e., put the corresponding output driver in a
hi-impedance mode). Clearing a TRISB bit (=0) will
make the corresponding PORTB pin an output ( i.e.,
put the contents of the output latch on the selected pin).
Read-modify-write operations on the LATB register
read and write the latched output value for PORTB.
EXAMPLE 8-2:
FIGURE 8-4:
2000 Microchip Technology Inc.
CLRF
CLRF
MOVLW
MOVWF
Data Bus
WR LATB
or
WR PORTB
WR TRISB
RBPU
RBx/INTx
Set RBIF
Note 1:
From other
RB7:RB4 pins
(2)
2:
PORTB, TRISB and LATB Registers
PORTB
LATB
0xCF
TRISB
I/O pins have diode protection to V
To enable weak pull-ups, set the appropriate TRIS
bit(s) and clear the RBPU bit (INTCON2 register).
RD TRISB
RD LATB
RD PORTB
Data Latch
TRIS Latch
RB7:RB4 PINS BLOCK
DIAGRAM
D
D
CK
CK
INITIALIZING PORTB
; Initialize PORTB by
; clearing output
; data latches
; Alternate method
; to clear output
; data latches
; Value used to
; initialize data
; direction
; Set RB3:RB0 as inputs
; RB5:RB4 as outputs
; RB7:RB6 as inputs
Q
Q
Q
Q
Latch
EN
EN
D
D
TTL
Input
Buffer
DD
and V
RD PORTB
V
P
Advanced Information
DD
Weak
Pull-up
I/O pin
SS
Buffer
.
Q1
Q3
ST
(1)
Each of the PORTB pins has a weak internal pull-up. A
single control bit can turn on all the pull-ups. This is per-
formed by clearing bit RBPU (INTCON2 register). The
weak pull-up is automatically turned off when the port
pin is configured as an output. The pull-ups are dis-
abled on a Power-on Reset.
Four
interrupt-on-change feature. Only pins configured as
inputs can cause this interrupt to occur (i.e., any
RB7:RB4 pin configured as an output is excluded from
the interrupt-on-change comparison). The input pins
(of RB7:RB4) are compared with the old value latched
on the last read of PORTB. The “mismatch” outputs of
RB7:RB4 are OR’d together to generate the RB Port
Change Interrupt with flag bit RBIF (INTCON register).
This interrupt can wake the device from SLEEP. The
user, in the Interrupt Service Routine, can clear the
interrupt in the following manner:
a)
b)
A mismatch condition will continue to set flag bit RBIF.
Reading PORTB will end the mismatch condition and
allow flag bit RBIF to be cleared.
The interrupt-on-change feature is recommended for
wake-up on key depression operation and operations
where PORTB is only used for the interrupt on change
feature. Polling of PORTB is not recommended while
using the interrupt-on-change feature.
FIGURE 8-5:
Data Bus
WR Port
WR TRIS
RBx/INTx
RBPU
Note 1:
Any read or write of PORTB (except with the
MOVFF instruction). This will end the mismatch
condition.
Clear flag bit RBIF.
of
2:
(2)
PORTB’s
I/O pins have diode protection to V
To enable weak pull-ups, set the appropriate TRIS
bit(s) and clear the RBPU bit (INTCON2 register).
RB3:RB0 PINS BLOCK
DIAGRAM
RD TRIS
RD Port
Data Latch
TRIS Latch
D
D
CK
CK
Schmitt Trigger
Buffer
pins,
PIC18CXX8
Q
Q
RB7:RB4,
Q
DS30475A-page 91
EN
D
DD
TTL
Input
Buffer
and V
V
P
RD Port
have
DD
Weak
Pull-up
SS
I/O Pin
.
(1)
an
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