PIC18C658-E/PT Microchip Technology, PIC18C658-E/PT Datasheet - Page 293
![IC MCU OTP 16KX16 CAN 64TQFP](/photos/6/81/68123/c04-066_pf_sml.jpg)
PIC18C658-E/PT
Manufacturer Part Number
PIC18C658-E/PT
Description
IC MCU OTP 16KX16 CAN 64TQFP
Manufacturer
Microchip Technology
Series
PIC® 18Cr
Datasheets
1.PIC16F616T-ISL.pdf
(8 pages)
2.PIC16C770-ISO.pdf
(8 pages)
3.PIC18C658-IPT.pdf
(366 pages)
4.PIC18C658-IPT.pdf
(16 pages)
5.PIC18C658-IPT.pdf
(16 pages)
6.PIC18C658-IPT.pdf
(16 pages)
Specifications of PIC18C658-E/PT
Core Processor
PIC
Core Size
8-Bit
Speed
40MHz
Connectivity
CAN, I²C, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, LVD, POR, PWM, WDT
Number Of I /o
52
Program Memory Size
32KB (16K x 16)
Program Memory Type
OTP
Ram Size
1.5K x 8
Voltage - Supply (vcc/vdd)
4.2 V ~ 5.5 V
Data Converters
A/D 12x10b
Oscillator Type
External
Operating Temperature
-40°C ~ 125°C
Package / Case
64-TFQFP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Other names
PIC18C658E/PT
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
PIC18C658-E/PT
Manufacturer:
Microchip Technology
Quantity:
10 000
- PIC16F616T-ISL PDF datasheet
- PIC16C770-ISO PDF datasheet #2
- PIC18C658-IPT PDF datasheet #3
- PIC18C658-IPT PDF datasheet #4
- PIC18C658-IPT PDF datasheet #5
- PIC18C658-IPT PDF datasheet #6
- Current page: 293 of 366
- Download datasheet (7Mb)
RETURN
Syntax:
Operands:
Operation:
Status Affected:
Encoding:
Description:
Words:
Cycles:
Q Cycle Activity:
Example:
2000 Microchip Technology Inc.
After Call
Before Instruction
After Instruction
operation
Decode
No
PC
WRG
STATUS =
BSR
WREG
STATUS =
BSR
PC
Q1
=
=
=
=
=
=
operation
operation
Return from Subroutine
[ label ]
s
(TOS)
if s = 1
(WS)
(STATUSS)
(BSRS)
PCLATU, PCLATH are unchanged
None
Return from subroutine. The
stack is popped and the top of the
stack (TOS) is loaded into the
program counter. If ’s’ = 1, the
contents of the shadow registers
WS, STATUSS and BSRS are
loaded into their corresponding
registers, WREG, STATUS and
BSR. If ’s’ = 0, no update of
these registers occurs (default).
1
2
RETURN
RETURN FAST
0000
No
No
Q2
TOS
0x04
0x00
0x00
0x04
0x00
0x00
TOS
[0,1]
W,
PC,
RETURN [s]
0000
BSR,
operation
Process
Data
No
STATUS,
Q3
0001
Pop PC from
Advanced Information
operation
stack
No
Q4
001s
RLCF
Syntax:
Operands:
Operation:
Status Affected:
Encoding:
Description:
Words:
Cycles:
Q Cycle Activity:
Example:
Before Instruction
After Instruction
Decode
REG
C
N
Z
REG
WREG
C
N
Z
Q1
=
=
=
=
=
=
=
=
=
register ’f’
Rotate Left f through Carry
[ label ] RLCF
0
d
a
(f<n>)
(f<7>)
(C)
C,N,Z
The contents of register 'f' are
rotated one bit to the left through
the Carry Flag. If 'd' is 0 the result is
placed in WREG. If 'd' is 1 the
result is stored back in register 'f'
(default). If ’a’ is 0, the Access
Bank will be selected, overriding
the BSR value. If ’a’ is 1, the Bank
will be selected as per the BSR
value.
1
1
RLCF
Read
Q2
0011
1110 0110
0
?
?
1110 0110
1100 1100
1
1
0
f
PIC18CXX8
[0,1]
[0,1]
C
dest<0>
255
dest<n+1>,
C,
01da
Process
REG, W
Data
Q3
register f
DS30475A-page 293
f [ ,d [,a] ]
ffff
destination
Write to
Q4
ffff
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