PIC18C442-E/L Microchip Technology, PIC18C442-E/L Datasheet - Page 83

• Manufacturer Part Number: PIC18C442-E/L
• Description: IC MCU OTP 8KX16 A/D 44PLCC
• Manufacturer: Microchip Technology
• Series: PIC® 18Cr

Specifications of PIC18C442-E/L

• Core Processor: PIC
• Core Size: 8-Bit
• Speed: 40MHz
• Connectivity: I²C, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, LVD, POR, PWM, WDT
• Number Of I /o: 33
• Program Memory Size: 16KB (8K x 16)
• Program Memory Type: OTP
• Ram Size: 512 x 8
• Voltage - Supply (vcc/vdd): 4.2 V ~ 5.5 V
• Data Converters: A/D 8x10b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 125°C
• Package / Case: 44-PLCC
• For Use With: DVA16XL441 - ADAPTER DEVICE ICE 44PLCC
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Other names: PIC18C442E/L

FIGURE 8-5:
FIGURE 8-6:
2001 Microchip Technology Inc.
Note 1: I/O pins have diode protection to V
Note 1: I/O pin has diode protection to V
2: To enable weak pull-ups, set the appropriate TRIS bit(s) and clear the RBPU bit (OPTION_REG<7>).
2: To enable weak pull-ups, set the appropriate DDR bit(s) and clear the RBPU bit (INTCON2<7>).
3: The CCP2 input/output is multiplexed with RB3, if the CCP2MX bit is enabled (=’0’) in the configuration register.
CCP Output
CCP2 Input
Enable
CCP Output
WR TRISB
RD PORTB
Data Bus
WR LATB or
WR PORTB
RBPU
BLOCK DIAGRAM OF RB2:RB0 PINS
BLOCK DIAGRAM OF RB3
(2)
CCP2MX
(3)
(3)
Data Bus
WR TRIS
WR Port
RB0/INT
RBPU
(3)
(2)
Schmitt Trigger
Buffer
RD TRISB
RD LATB
RD PORTB
TRIS Latch
Data Latch
D
D
CK
CK
DD
DD
and V
and V
Q
Q
RD TRIS
RD Port
TRIS Latch
Data Latch
CCP2MX = 0
D
D
CK
CK
SS
Schmitt Trigger Buffer
SS
.
.
Q
Q
Q
1
0
EN
D
Q
EN
TTL
Input
Buffer
D
V
P
RD Port
DD
Weak
Pull-up
V
V
N
P
SS
DD
I/O pin
TTL
Input
Buffer
(1)
V
P
DD
PIC18CXX2
Weak
Pull-up
I/O pin
(1)
DS39026C-page 81