PIC18C442-E/L Microchip Technology, PIC18C442-E/L Datasheet - Page 169

IC MCU OTP 8KX16 A/D 44PLCC

PIC18C442-E/L

Manufacturer Part Number
PIC18C442-E/L
Description
IC MCU OTP 8KX16 A/D 44PLCC
Manufacturer
Microchip Technology
Series
PIC® 18Cr

Specifications of PIC18C442-E/L

Core Processor
PIC
Core Size
8-Bit
Speed
40MHz
Connectivity
I²C, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, LVD, POR, PWM, WDT
Number Of I /o
33
Program Memory Size
16KB (8K x 16)
Program Memory Type
OTP
Ram Size
512 x 8
Voltage - Supply (vcc/vdd)
4.2 V ~ 5.5 V
Data Converters
A/D 8x10b
Oscillator Type
External
Operating Temperature
-40°C ~ 125°C
Package / Case
44-PLCC
For Use With
DVA16XL441 - ADAPTER DEVICE ICE 44PLCC
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Other names
PIC18C442E/L

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
PIC18C442-E/L
Manufacturer:
Microchip Technology
Quantity:
10 000
The analog reference voltage is software selectable to
either the device’s positive and negative supply voltage
(V
V
The A/D converter has a unique feature of being able
to operate while the device is in SLEEP mode. To oper-
ate in SLEEP, the A/D conversion clock must be
derived from the A/D’s internal RC oscillator.
The output of the sample and hold is the input into the
converter, which generates the result via successive
approximation.
A device RESET forces all registers to their RESET
state. This forces the A/D module to be turned off and
any conversion is aborted.
FIGURE 16-1:
REF
DD
2000 Microchip Technology Inc.
+ pin and RA2/AN2/V
and V
Converter
10-bit
SS
A/D
) or the voltage level on the RA3/AN3/
Reference
voltage
A/D BLOCK DIAGRAM
REF
-.
V
V
REF
REF
-
+
(Input Voltage)
V
AIN
PCFG0
V
DD
V
Each port pin associated with the A/D converter can be
configured as an analog input (RA3 can also be a volt-
age reference) or as a digital I/O.
The ADRESH and ADRESL registers contain the result
of the A/D conversion. When the A/D conversion is
complete, the result is loaded into the ADRESH/
ADRESL registers, the GO/DONE bit (ADCON0<2>) is
cleared, and A/D interrupt flag bit ADIF is set. The block
diagram of the A/D module is shown in Figure 16-1.
SS
CHS2:CHS0
111
110
101
100
011
010
001
000
PIC18CXX2
DS39026C-page 167
AN1
AN7
AN2
AN0
AN6
AN5
AN4
AN3

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