PIC18C442-E/L Microchip Technology, PIC18C442-E/L Datasheet - Page 106

• Manufacturer Part Number: PIC18C442-E/L
• Description: IC MCU OTP 8KX16 A/D 44PLCC
• Manufacturer: Microchip Technology
• Series: PIC® 18Cr

Specifications of PIC18C442-E/L

• Core Processor: PIC
• Core Size: 8-Bit
• Speed: 40MHz
• Connectivity: I²C, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, LVD, POR, PWM, WDT
• Number Of I /o: 33
• Program Memory Size: 16KB (8K x 16)
• Program Memory Type: OTP
• Ram Size: 512 x 8
• Voltage - Supply (vcc/vdd): 4.2 V ~ 5.5 V
• Data Converters: A/D 8x10b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 125°C
• Package / Case: 44-PLCC
• For Use With: DVA16XL441 - ADAPTER DEVICE ICE 44PLCC
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Other names: PIC18C442E/L

PIC18CXX2
12.1
Timer3 can operate in one of these modes:
• As a timer
• As a synchronous counter
• As an asynchronous counter
The operating mode is determined by the clock select
bit, TMR3CS (T3CON<1>).
FIGURE 12-1:
FIGURE 12-2:
DS39206C-page 104
Note 1: When enable bit T1OSCEN is cleared, the inverter and feedback resistor are turned off. This eliminates power drain.
Set TMR3IF Flag bit
on Overflow
Note 1: When enable bit T1OSCEN is cleared, the inverter and feedback resistor are turned off. This eliminates power drain.
T1OSO/
T13CKI
T1OSI
Timer3 Operation
Data Bus<7:0>
Write TMR3L
Read TMR3L
T1OSO/
T13CKI
T1OSI
TMR3IF
Overflow
Interrupt
Flag bit
TIMER3 BLOCK DIAGRAM
TIMER3 BLOCK DIAGRAM CONFIGURED IN 16-BIT READ/WRITE MODE
T1OSC
8
TMR3H
T1OSC
High Byte
TMR3H
Timer3
8
To Timer1 Clock Input
Enable
Oscillator
T1OSCEN
8
TMR3
TMR3L
Oscillator
Enable
T1OSCEN
(1)
8
CLR
TMR3L
(1)
(3)
Clock
Internal
F
CLR
OSC
/4
TMR3ON
On/Off
F
Internal
Clock
TMR3CS
OSC
When TMR3CS = 0, Timer3 increments every instruc-
tion cycle. When TMR3CS = 1, Timer3 increments on
every rising edge of the Timer1 external clock input or
the Timer1 oscillator, if enabled.
When the Timer1 oscillator is enabled (T1OSCEN is
set), the RC1/T1OSI and RC0/T1OSO/T1CKI pins
become inputs. That is, the TRISC<1:0> value is
ignored.
Timer3 also has an internal “RESET input”. This
RESET can be generated by the CCP module
(Section 12.0).
CCP Special Trigger
T3CCPx
1
0
/4
TMR3ON
On/Off
T3CKPS1:T3CKPS0
TMR3CS
1
0
T3SYNC
Prescaler
1, 2, 4, 8
T3CCPx
CCP Special Trigger
T3CKPS1:T3CKPS0
0
1
2
T3SYNC
Prescaler
1, 2, 4, 8
0
1
2
2001 Microchip Technology Inc.
Synchronized
Clock Input
Synchronize
SLEEP Input
det
Synchronized
Clock Input
Synchronize
SLEEP Input
det