ATMEGA323-8AI Atmel, ATMEGA323-8AI Datasheet - Page 86
![IC AVR MCU 32K 8MHZ IND 44TQFP](/photos/6/70/67042/313-44-tqfp_sml.jpg)
ATMEGA323-8AI
Manufacturer Part Number
ATMEGA323-8AI
Description
IC AVR MCU 32K 8MHZ IND 44TQFP
Manufacturer
Atmel
Series
AVR® ATmegar
Datasheet
1.ATMEGA323L-4PC.pdf
(247 pages)
Specifications of ATMEGA323-8AI
Core Processor
AVR
Core Size
8-Bit
Speed
8MHz
Connectivity
I²C, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, POR, PWM, WDT
Number Of I /o
32
Program Memory Size
32KB (16K x 16)
Program Memory Type
FLASH
Eeprom Size
1K x 8
Ram Size
2K x 8
Voltage - Supply (vcc/vdd)
4.5 V ~ 5.5 V
Data Converters
A/D 8x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
44-TQFP, 44-VQFP
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Other names
ATMEGA3238AI
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Receive Compete Flag and
Interrupt
Receiver Error Flags
86
ATmega323(L)
The receive function example reads all the I/O Registers into the Register File before
any computation is done. This gives an optimal receive buffer utilization since the buffer
location read will be free to accept new data as early as possible.
The USART Receiver has one flag that indicates the Receiver state.
The Receive Complete (RXC) Flag indicates if there are unread data present in the
receive buffer. This flag is one when unread data exist in the receive buffer, and zero
when the receive buffer is empty (i.e. does not contain any unread data). If the Receiver
is disabled (RXEN = 0), the receive buffer will be flushed and consequently the RXC bit
will become zero.
When the Receive Complete Interrupt Enable (RXCIE) in UCSRB is set, the USART
Receive Complete Interrupt will be executed as long as the RXC Flag is set (provided
that global interrupts are enabled). When interrupt-driven data reception is used, the
receive complete routine must read the received data from UDR in order to clear the
RXC Flag, otherwise a new interrupt will occur once the interrupt routine terminates.
The USART Receiver has three Error Flags: Frame Error (FE), Data OverRun (DOR)
and Parity Enable (PE). All can be accessed by reading UCSRA. Common for the Error
Flags is that they are located in the receive buffer together with the frame for which they
indicate the error status. Due to the buffering of the Error Flags, the UCSRA must be
read before the receive buffer (UDR), since reading the UDR I/O location changes the
buffer read location. Another equality for the Error Flags is that they can not be altered
by software doing a write to the flag location. However, all flags must be set to zero
when the UCSRA is written for upward compatibility of future USART implementations.
None of the Error Flags can generate interrupts.
The Frame Error (FE) Flag indicates the state of the first stop bit of the next readable
frame stored in the receive buffer. The FE Flag is zero when the stop bit was correctly
read (as one), and the FE Flag will be one when the stop bit was incorrect (zero). This
flag can be used for detecting out-of-sync conditions, detecting break conditions and
protocol handling. The FE Flag is not affected by the setting of the USBS bit in UCSRC
since the Receiver ignores all, except for the first, stop bits. For compatibility with future
devices, always set this bit to zero when writing to UCSRA.
The Data OverRun (DOR) Flag indicates data loss due to a Receiver buffer full condi-
tion. A Data OverRun occurs when the receive buffer is full (two characters), it is a new
character waiting in the Receive Shift Register, and a new start bit is detected. If the
DOR Flag is set there was one or more serial frame lost between the frame last read
from UDR, and the next frame read from UDR. For compatibility with future devices,
always set this bit to zero when writing to UCSRA. The DOR Flag is cleared when the
frame received was successfully moved from the Shift Register to the receive buffer.
The Parity Error (PE) Flag indicates that the next frame in the receive buffer did have an
parity error when received. If parity check is not enabled the PE bit will always be read
zero. For compatibility with future devices, always set this bit to zero when writing to
UCSRA. For more details see “Parity Bit Calculation” on page 79 and “Parity Checker”
on page 87.
1457G–AVR–09/03
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