ATMEGA323-8AI Atmel, ATMEGA323-8AI Datasheet - Page 167
![IC AVR MCU 32K 8MHZ IND 44TQFP](/photos/6/70/67042/313-44-tqfp_sml.jpg)
ATMEGA323-8AI
Manufacturer Part Number
ATMEGA323-8AI
Description
IC AVR MCU 32K 8MHZ IND 44TQFP
Manufacturer
Atmel
Series
AVR® ATmegar
Datasheet
1.ATMEGA323L-4PC.pdf
(247 pages)
Specifications of ATMEGA323-8AI
Core Processor
AVR
Core Size
8-Bit
Speed
8MHz
Connectivity
I²C, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, POR, PWM, WDT
Number Of I /o
32
Program Memory Size
32KB (16K x 16)
Program Memory Type
FLASH
Eeprom Size
1K x 8
Ram Size
2K x 8
Voltage - Supply (vcc/vdd)
4.5 V ~ 5.5 V
Data Converters
A/D 8x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
44-TQFP, 44-VQFP
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Other names
ATMEGA3238AI
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IDCODE; $1
SAMPLE_PRELOAD; $2
AVR_RESET; $C
BYPASS; $F
1457G–AVR–09/03
•
Optional JTAG instruction selecting the 32 bit ID Register as Data Register. The ID Reg-
ister consists of a version number, a device number and the manufacturer code chosen
by JEDEC. This is the default instruction after Power-up.
The active states are:
•
•
Mandatory JTAG instruction for pre-loading the output latches and taking a snap-shot of
the input/output pins without affecting the system operation. However, the output latches
are not connected to the pins. The Boundary-Scan Chain is selected as Data Register.
The active states are:
•
•
•
The AVR specific public JTAG instruction for forcing the AVR device into the Reset
mode or releasing the JTAG Reset source. The TAP controller is not reset by this
instruction. The one bit Reset Register is selected as Data Register. Note that the reset
will be active as long as there is a logic 'one' in the Reset Chain. The output from this
chain is not latched.
The active states are:
•
Mandatory JTAG instruction selecting the Bypass Register for Data Register.
The active states are:
•
•
Update-DR: Data from the scan chain is applied to output pins.
Capture-DR: Data in the IDCODE Register is sampled into the Boundary-Scan
Chain.
Shift-DR: The IDCODE scan chain is shifted by the TCK input.
Capture-DR: Data on the external pins are sampled into the Boundary-Scan Chain.
Shift-DR: The Boundary-Scan Chain is shifted by the TCK input.
Update-DR: Data from the Boundary-Scan chain is applied to the output latches.
However, the output latches are not connected to the pins.
Shift-DR: The Reset Register is shifted by the TCK input.
Capture-DR: Loads a logic “0” into the Bypass Register.
Shift-DR: The Bypass Register cell between TDI and TDO is shifted.
ATmega323(L)
167
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