ATMEGA323-8AI Atmel, ATMEGA323-8AI Datasheet - Page 102
![IC AVR MCU 32K 8MHZ IND 44TQFP](/photos/6/70/67042/313-44-tqfp_sml.jpg)
ATMEGA323-8AI
Manufacturer Part Number
ATMEGA323-8AI
Description
IC AVR MCU 32K 8MHZ IND 44TQFP
Manufacturer
Atmel
Series
AVR® ATmegar
Datasheet
1.ATMEGA323L-4PC.pdf
(247 pages)
Specifications of ATMEGA323-8AI
Core Processor
AVR
Core Size
8-Bit
Speed
8MHz
Connectivity
I²C, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, POR, PWM, WDT
Number Of I /o
32
Program Memory Size
32KB (16K x 16)
Program Memory Type
FLASH
Eeprom Size
1K x 8
Ram Size
2K x 8
Voltage - Supply (vcc/vdd)
4.5 V ~ 5.5 V
Data Converters
A/D 8x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
44-TQFP, 44-VQFP
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Other names
ATMEGA3238AI
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Two-wire Serial
Interface (Byte
Oriented)
102
ATmega323(L)
The Two-wire Serial Interface supports bi-directional serial communication. It is
designed primarily for simple but efficient integrated circuit (IC) control. The system is
comprised of two lines, SCL (Serial Clock) and SDA (Serial Data) that carry information
between the ICs connected to them. Various communication configurations can be
designed using this bus. Figure 52 shows a typical Two-wire Serial Bus configuration.
Any device connected to the bus can be Master or Slave. Note that all AVR devices con-
nected to the bus must be powered to allow any bus operation.
Figure 52. Two-wire Serial Bus Configuration
The Two-wire Serial Interface supports Master/Slave and Transmitter/Receiver opera-
tion at up to 400 kHz bus clock rate. The Two-wire Serial Interface has hardware
support for 7-bit addressing. When the Two-wire Serial Interface is enabled (TWEN in
TWCR is set), a glitch filter is enabled for the input signals from the pins PC0 (SCL) and
PC1 (SDA), and the output from these pins is slew-rate controlled. The Two-wire Serial
Interface is byte oriented. The operation of the Two-wire Serial Bus is shown as a pulse
diagram in Figure 53, including the START and STOP conditions and generation of ACK
signal by the bus Receiver.
Figure 53. Two-wire Serial Bus Timing Diagram
The block diagram of the Two-wire Serial Interface is shown in Figure 54.
SDA
SCL
CONDITION
Device 1
START
MSB
1
2
Device 2
7
R/W
BIT
8
Device 3
ACK
9
FROM RECEIVER
ACKNOWLEDGE
.......
1
2
Device n
8
ACK
9
R1
R2
REPEATED START CONDIT
STOP CONDITION
1457G–AVR–09/03
V
SCL
SDA
CC
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